Chip Delayering with Gyroscopic Position Control for Failure Analysis
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Solution Overview
Problem
The challenge of efficiently and precisely delayering complex semiconductor chips, such as finFET chips, to detect electrical faults and failures is exacerbated by shrinking feature dimensions and increasing structural complexity, leading to challenges in reproducibility, time consumption, and the need for highly skilled professionals.
Innovation Solution
A system utilizing gyroscopic stabilization and piezoelectric motors, integrated with machine learning and feedback loops, for precise and automated delayering of chips, enabling rapid and reproducible detection of failures and defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual delayering techniques are used for complex semiconductor chips, then detection of electrical faults and failures can be performed, but the process is time-consuming and requires highly skilled professionals
Solution Approach 1:
The patent replaces manual mechanical delayering operations with an automated system that uses a polishing head guided by image recognition and control algorithms. The system captures images of the chip, processes them to determine polishing parameters, and automatically controls the polishing head to remove layers systematically, eliminating the need for skilled manual operation while maintaining precision.
Solution Approach 2:
The system performs self-adjustment by capturing images of the chip during delayering, processing these images to determine the current state, and automatically adjusting polishing parameters based on the image analysis. This closed-loop control enables the system to self-correct and maintain optimal performance without continuous human intervention.
2Productivity
If feature dimensions are shrunk to increase integration density, then more devices can be packed on the chip, but failure analysis becomes more challenging
Solution Approach 1:
The patent replaces manual inspection and delayering with an automated optical inspection system that captures high-resolution images of the chip layers. The image processing algorithms automatically analyze the captured images to detect defects and failures in the miniaturized structures, making failure analysis feasible despite the reduced feature dimensions.
Solution Approach 2:
The system transitions from direct physical manipulation to optical field-based inspection and control. By using optical imaging to capture chip layer information and processing these images computationally, the system can analyze sub-micron features without physical contact, overcoming the limitations imposed by shrinking feature dimensions.
3Adaptability or versatility
If complex 3D architectures are implemented to increase functionality, then device capabilities are enhanced, but the number of wiring layers and structure complexity increase
Solution Approach 1:
The patent applies segmentation by systematically dividing the delayering process into discrete steps, with each step removing a specific layer or portion of the chip. The image recognition system identifies layer boundaries and guides the polishing head to remove material in controlled segments, making the analysis of complex multi-layer architectures manageable and systematic.
Solution Approach 2:
The system performs preliminary imaging and analysis before each polishing operation to determine the optimal polishing parameters and depth. By pre-planning each delayering step based on image analysis, the system can systematically navigate through complex wiring layers without causing damage or missing critical features.
4Productivity
If automated delayering systems are implemented to reduce time consumption, then productivity increases, but system complexity and cost increase
Solution Approach 1:
The patent implements a multi-functional system where the same imaging and control hardware serves multiple purposes: capturing chip images, analyzing defect patterns, determining polishing parameters, and guiding the polishing head. This universal platform approach reduces overall system complexity compared to having separate specialized systems for each function.
Solution Approach 2:
The system uses real-time feedback from image capture during delayering to continuously adjust polishing parameters. The control algorithm processes images captured during the process and automatically modifies polishing depth, speed, and path based on the observed chip state, enabling adaptive control that simplifies the automation of complex delayering tasks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system significantly reduces the time required to identify failures, enhances reproducibility, and lowers costs by automating the delayering process, allowing for wider user access and faster innovation in chip development.
Implementation Method 1
a vacuum stage being connected to a sample, the vacuum stage being configured to maintain a position of the sample to a polishing table
Implementation Method 2
receiving information from a gyroscope unit
Data Source
AI summary
Embodiments are related to providing systematic delayering of chips, such as finFET chips, along with performing field failure and material investigation. Techniques include receiving information from a gyroscope unit, a vacuum stage being connected to a sample, the vacuum stage being configured to maintain a position of the sample to a polishing table. Techniques include adjusting the position of the sample based, at least in part, on the information received from the gyroscope unit.