Chip Description System for Seamless Design Data Management
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Solution Overview
Problem
Traditional semiconductor chip design representations in Register Transfer Language (RTL) source files lack information on non-functional aspects such as clock rates, leading to a loss of design information during the design process, which complicates communication and implementation.
Innovation Solution
An automated design process and chip description system that generates a modified design output including physical and non-physical attributes, using a transparent user-creatable object space to integrate design, tool, and process objects, ensuring seamless communication and improved data management across the design cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If traditional functional descriptions (RTL source files) are used to represent chip design, then the design can be modeled and tested, but non-functional aspects such as clock rates and manufacturing characteristics are lost
Solution Approach 1:
The patent merges functional descriptions (RTL source files) and non-functional attributes (constraint files, metadata) into a unified design representation system. The chip description system integrates multiple data types including functional behavior, physical attributes, manufacturing characteristics, and timing information into a single coherent model, eliminating the need for separate constraint files and documentation.
Solution Approach 2:
The chip description system serves multiple functions simultaneously: it describes functional behavior, stores non-functional attributes, provides manufacturing constraints, and enables automated design flow. This multi-functional approach replaces the traditional fragmented system where separate tools handled functional verification, constraint checking, and manufacturing optimization.
2Loss of information
If non-functional aspects are described in separate constraint files and documents, then design information is preserved, but communication and coordination between design steps becomes complicated
Solution Approach 1:
The patent combines functional and non-functional information into a single integrated chip description system. Design objects automatically carry both their functional behavior and non-functional attributes within the same data structure, eliminating the need for separate constraint files and reducing communication overhead between design tools and team members.
Solution Approach 2:
The chip description system acts as an intermediary layer between functional verification tools and manufacturing constraints. This unified representation serves as a common language that automated tools can process without requiring complex interactions between separate constraint files, scripts, and documentation systems.
3Loss of information
If design information is scattered across multiple files and databases, then comprehensive design coverage is achieved, but data management and consistency become difficult
Solution Approach 1:
The patent segments design information into organized data structures within the chip description system. Design objects are divided into functional components and non-functional attributes, with each segment maintaining clear relationships through standardized interfaces. This structured segmentation enables comprehensive coverage while simplifying data management through automated consistency checking.
Solution Approach 2:
The chip description system provides a universal data management framework that handles functional verification, manufacturing constraints, timing information, and physical attributes within a single integrated structure. This unified approach replaces the fragmented multi-file system with a consistent data model that simplifies data management while maintaining comprehensive design coverage.
Data Source
AI summary
An automated design process and chip description system is disclosed. The automated design process and chip description system compensates for the loss in design information that occurs when the design is represented in traditional functional descriptions. The automated design process includes the steps of processing a design definition according to a functional description and generating a modified design output such that communication between design process steps is seamless. The chip description system comprises a storage element and a functional element, wherein a first design object couples to a second design object such that the coupling uses at least one functional element to access one or more storage elements usable by the chip description system. A data structure for use in a chip description system is also disclosed and comprises a plurality of design objects, a plurality of tool objects interactively coupled with the design objects, a plurality of process objects interactively coupled with the tool objects and the design objects, a plurality of people objects interactively coupled with the process objects, the design objects and the tool objects, wherein the interactive coupling provides improved data management for a plurality of design files.