Semiconductor Chip Design Error Detection via Data Matching
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Solution Overview
Problem
The design process for semiconductor chip input/output interfaces is time-consuming and unreliable, as designers must manually verify the arrangement of cells and routing, leading to potential errors and increased expenses.
Innovation Solution
A method and apparatus that automatically detect design errors in semiconductor chip input/output interfaces by acquiring data on cell arrangements and routing information, merging this data to identify errors such as short errors, float errors, and different type library errors, and outputting a verification result to correct these issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a designer manually designs and verifies input/output cells directly, then the design process can be completed, but the verification process is unreliable and time-consuming
Solution Approach 1:
The design verification system automatically checks the arrangement of input/output cells and routing without requiring manual designer intervention. The system serves itself by performing error detection, short error detection, float error detection, and library error detection autonomously, eliminating the time-consuming and unreliable manual verification process while maintaining high reliability
Solution Approach 2:
The patent replaces the manual mechanical verification process with an automated computational system. Instead of designers manually checking cell arrangements and routing, a computing device executes automated error detection algorithms that systematically analyze the design data, power line data, and routing information to identify errors, thereby substituting human effort with automated mechanical computation
2Reliability
If manual verification of cell arrangement and routing is performed, then design errors can be detected, but expenses increase and reliability remains low
Solution Approach 1:
The automated verification system performs error detection without requiring manual designer intervention for each check. The system autonomously executes multiple verification tasks including error detection, short error detection, float error detection, and library error detection, making the design process more efficient and reliable while reducing expenses associated with manual verification
3Measurement precision
If direct designer intervention is used for verifying input/output interface design, then design accuracy can be maintained, but the process becomes time-consuming and expensive
Solution Approach 1:
The patent replaces manual designer verification with automated computational verification systems. The computing device executes automated algorithms that perform error detection, short error detection, float error detection, and library error detection with high precision, maintaining design accuracy while dramatically improving productivity by eliminating time-consuming manual processes
Solution Approach 2:
The verification system automatically detects errors without requiring continuous manual intervention. The system self-services by autonomously analyzing design data, comparing it against power line data and routing information, and identifying errors across multiple categories, thereby maintaining high detection accuracy while significantly increasing verification productivity
Data Source
AI summary
A method of designing a semiconductor chip includes: acquiring first data including information about arrangement of a plurality of cells on the semiconductor chip; acquiring second data including information about routing between the plurality of cells and power and signal lines; and outputting a verification result by detecting an error of arrangement of the plurality of cells based on matching of the first data and the second data.