Statistical Model Predictor for Chip Design Layout Defect Discovery
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in accurately predicting and discovering unknown problematic circuit patterns in chip design layouts, leading to systematic defects and yield limitations due to distortion from optical, chemical, and etching processes, as well as limitations in existing OPC and LPC models.
Innovation Solution
A system comprising a critical signature library, a statistical model creator, and a statistical model-based predictor that stores known problematic circuit patterns with associated physical and simulation data, extracts features, and creates models to predict unknown problematic patterns by dividing data sets and applying them to candidate patterns generated from chip design layouts or wafer inspections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If OPC and LPC models are used to predict hot spots, then pattern distortion can be corrected, but unknown problematic patterns may be missed leading to systematic defects
Solution Approach 1:
The system performs preliminary action by collecting and analyzing manufacturing defect data before final pattern prediction. Defect data from multiple sources (optical inspection, e-beam inspection, metrology tools) is gathered and processed in advance to train the machine learning model, enabling it to predict both known and unknown problematic patterns with higher accuracy
Solution Approach 2:
A machine learning model serves as an intermediary between raw defect data and pattern prediction results. The model learns from historical defect data and acts as a mediator to identify problematic patterns that traditional OPC/LPC models miss, bridging the gap between known and unknown defect types
2Difficulty of detecting and measuring
If the number of predicted hot spots is increased, then thoroughness of detection improves, but wafer inspector overload occurs
Solution Approach 1:
The system applies partial action by using machine learning to prioritize and select the most critical hot spots for inspection. Instead of inspecting all predicted hot spots equally, the system identifies and focuses on the subset of patterns with highest defect probability, reducing inspection load while maintaining detection thoroughness
Solution Approach 2:
The system implements feedback by using actual inspection results and defect data to continuously retrain and improve the machine learning model. The model learns from past inspection outcomes, refining its predictions to reduce false positives and optimize the balance between detection thoroughness and inspection efficiency
3Measurement precision
If traditional LPC simulation is used, then known problematic patterns can be identified, but new circuit patterns in design revisions are not covered
Solution Approach 1:
The system changes parameters by transitioning from rule-based LPC simulation parameters to data-driven machine learning parameters. The model learns patterns from actual manufacturing data rather than relying on pre-defined simulation parameters, enabling it to adapt to new circuit patterns and design revisions while maintaining prediction accuracy
Data Source
AI summary
A system includes a critical signature library for storing critical signature databases of chip design layouts in semiconductor manufacturing and a statistical model creator for creating statistical models based on the known problematic circuit patterns stored in the critical signature databases and a target specification based on deviation between physical measurement and simulation data or design data associated with the known problematic circuit patterns. The system further has a statistical model based predictor for predicting and discovering unknown problematic circuit patterns by applying the statistical models to a large number of candidate circuit patterns generated from a random layout generator, or extracted from the chip design layout based on hot spot sites determined by extended lithographic process check on the chip design layout or inspecting wafers manufactured with the chip design layout with an aggressive sensitivity setting.