Early Power Estimation in Chip Design via Logical Hierarchy Mapping
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Solution Overview
Problem
Current methods fail to optimally map logical hierarchies to physical hierarchies in semiconductor chip design, particularly due to difficulties in pin optimization, power estimation, and layout constraints, which complicates the transformation process across multiple hierarchy levels.
Innovation Solution
A process that involves simulating the logical hierarchy to generate a switching activity file, which is then used to map and estimate power consumption in the physical hierarchy, utilizing a name database to translate port activities from the logical to the physical hierarchy, allowing for early power estimation before final placement and wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If automatic mapping from logical hierarchy to physical hierarchy is performed, then layout and routing constraints are considered, but pin optimization and power estimation become difficult
Solution Approach 1:
The patent applies preliminary action by performing pin optimization and power estimation at the logical hierarchy level before the hierarchy transformation to physical hierarchy is completed. This allows optimization to be done when the logical structure is still clear and manageable, avoiding the complexity that arises during and after transformation to physical hierarchy with layout constraints.
Solution Approach 2:
The patent segments the design process into distinct phases: power estimation is performed on the logical hierarchy separately from the physical hierarchy transformation. This segmentation allows each phase to be optimized independently - power estimation on logical hierarchy using switching activity data, and later physical implementation with layout constraints - without the complexities of pin optimization interfering with early power analysis.
2Adaptability or versatility
If hierarchy transformation is applied multiple times at different levels, then layout flexibility is improved, but power estimation accuracy deteriorates
Solution Approach 1:
The patent performs power estimation as a preliminary action at the logical hierarchy level, before multiple hierarchy transformations are applied. This ensures power estimation is done when the logical structure is stable and can be accurately simulated, avoiding the uncertainty introduced by subsequent transformations to physical hierarchy at different levels.
Solution Approach 2:
The patent uses switching activity data as an intermediary to bridge the logical hierarchy and physical hierarchy. The switching activity is captured from logical hierarchy simulation and then used to estimate power in the physical hierarchy, serving as a mediator that maintains accuracy despite the transformations between different hierarchy levels.
3Measurement precision
If power estimation is delayed until final placement and wiring are complete, then accuracy is improved, but design iteration time increases
Solution Approach 1:
The patent performs preliminary power estimation at the logical hierarchy level using switching activity data from logical simulation, before final placement and wiring are completed. This provides early power feedback to designers, enabling power-related design decisions to be made earlier in the design process without waiting for final physical hierarchy completion.
Solution Approach 2:
The patent applies partial action by performing power estimation on a subset of the complete design information available - using logical hierarchy and switching activity data rather than waiting for complete physical hierarchy with all placement and wiring details. This partial estimation provides sufficient early feedback to guide design decisions while enabling faster iteration cycles.
Data Source
AI summary
A process is described to allow an early power estimate where switching activity provided by a simulation of a logical hierarchy in a chip design is accomplished by mapping ports in the physical hierarchy to ports in a logical hierarchy after hierarchy manipulation has been done. Power estimation is done using the switching activity from the simulation of the logical hierarchy mapped to the ports of the physical hierarchy. Early power estimation using results of the hierarchy manipulation is better than power estimation on the logical hierarchy because blocks and signals in the logical hierarchy may be replicated or merged during the hierarchy manipulation.