Chip Design Optimizing Circuit Performance Across PVT Conditions
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Solution Overview
Problem
Existing chip design methods fail to ensure consistent circuit performance across a wide range of process, voltage, and temperature (PVT) conditions, as they cannot guarantee that the circuit meets target specifications when operating outside the predetermined sign-off corners.
Innovation Solution
A method that involves analyzing delta cell delays and delta net delays to identify sensitivity critical paths and performing engineering change orders (ECOs) to optimize circuit design for various PVT conditions, ensuring stable operation across a wide range of PVT environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-corner sign-off flow is performed to ensure circuit performance in each PVT corner, then circuit reliability in sign-off corners is improved, but circuit performance cannot be guaranteed under conditions outside the sign-off corner
Solution Approach 1:
The patent performs preliminary sensitivity analysis on timing paths to identify critical paths before final sign-off. By analyzing delta cell delays and delta net delays across PVT corners, the method proactively identifies paths that may violate timing constraints under unstated PVT conditions, allowing designers to address these issues before manufacturing rather than discovering them later
Solution Approach 2:
The patent implements a feedback mechanism where sensitivity analysis results from multiple PVT corners are used to identify critical paths, which then guide engineering change orders (ECOs). The process feeds back into the design by using the identified sensitivity critical paths to prioritize ECO applications, ensuring that design modifications address the most vulnerable paths across the PVT space
2Measurement precision
If sensitivity analysis is performed on all paths in the integrated circuit, then detection accuracy of timing violations is improved, but computational complexity increases
Solution Approach 1:
The patent segments the large set of all timing paths into two categories: timing critical paths (identified through traditional STA) and sensitivity critical paths (identified through sensitivity analysis). This segmentation allows the methodology to focus computational resources on identifying the most critical paths rather than uniformly analyzing all paths, thereby reducing overall analysis complexity while maintaining detection accuracy for the most vulnerable paths
Solution Approach 2:
The patent applies different analysis depths and methods to different paths based on their characteristics. Timing critical paths receive traditional STA analysis, while sensitivity critical paths receive targeted sensitivity analysis using delta delays. This local differentiation of analysis quality allows efficient resource allocation, applying rigorous analysis only where needed rather than uniformly across all paths
Data Source
AI summary
A method of designing a chip having an integrated circuit is provided. The method includes obtaining delta cell delays and delta net delays according to a process, voltage, and temperature (PVT) corner change with respect to a plurality of cells and a plurality of nets forming the integrated circuit; analyzing sensitivity with respect to a delay according to the PVT corner change of a plurality of paths in the integrated circuit, by using the delta cell delays and the delta net delays; determining N-number of sensitivity-critical paths among the plurality of paths based on a result of the analysis, wherein N is an integer greater than or equal to 0; and performing an engineering change order (ECO) based on a result of the determination.