Chip Device Through-Chip Interconnect Impedance Matching

Solution Overview

Problem

Current chip-and-wire methods for monolithic microwave integrated circuits (MMICs) are costly and inefficient for high-volume, low-cost production, leading to signal degradation at higher frequencies due to impedance mismatch and the need for skilled labor, while traditional packages in plastic or molded enclosures further degrade performance.

Innovation Solution

The implementation of a chip device with a through-chip interconnect and a clearance region, along with tuning stubs, to provide electrical connections and impedance matching, using a low-cost alumina package and reflow process, allowing for surface mount technology that reduces signal degradation and extends frequency range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional chip-and-wire methods are used for MMIC assembly, then electrical connections are established, but signal degradation occurs at higher frequencies due to impedance mismatch and production costs increase

Engineering Contradiction:

Improvesignal qualityVSAvoidproduction cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent extracts the problematic wire bonding step from the traditional chip-and-wire assembly process. By removing the wire interconnect and replacing it with a direct chip-to-substrate mounting approach using an alumina package, the source of impedance mismatch and signal degradation is eliminated, while simplifying the manufacturing process

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the package material parameter from traditional plastic or molded enclosures to alumina (ceramic). This material substitution provides better electrical properties including improved impedance matching and reduced signal degradation at high frequencies, while maintaining structural integrity

Inventive Principle:

Principle #35Parameter changes

2Reliability

If traditional packages in plastic or molded enclosures are used, then device protection is provided, but performance degrades at higher frequencies

Engineering Contradiction:

Improvefrequency responseVSAvoidsignal degradation

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the package material parameter from traditional plastic or molded enclosures to alumina (ceramic). This material substitution provides better electrical properties including improved impedance matching and reduced signal degradation at high frequencies, while maintaining structural integrity

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs alumina ceramic as a composite material that combines the protective enclosure function with superior electrical properties. The alumina package serves dual purposes: mechanical protection of the chip and optimization of electrical performance through its inherent dielectric properties and impedance characteristics

Inventive Principle:

Principle #40Composite materials

3Adaptability or versatility

If voltage controlled oscillator modules are used in the frequency range of 0.5 to 8 GHz, then DC feed lines can be implemented, but the components become unusable at higher frequencies due to signal degradation

Engineering Contradiction:

Improvefrequency rangeVSAvoidsignal quality

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent changes the package material parameter from traditional plastic or molded enclosures to alumina (ceramic). This material substitution provides better electrical properties including improved impedance matching and reduced signal degradation at high frequencies, while maintaining structural integrity

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10461387B2Systems and methods for improved chip device performance

Publication Date: 2019.10.29 AVIAT U S

AI summary

Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assist in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assist in impedance matching.