Semiconductor Chip Chamfered Edge Dicing to Limit Active-Layer Cracks

Solution Overview

Problem

During the process of manufacturing semiconductor chips, external forces applied during wafer division can cause cracking in the active layer, leading to a shortened lifespan of the resulting device chips.

Innovation Solution

A semiconductor chip design featuring a protective layer covering the active layer, with a first chamfer extending from the active layer's edge and a modifier formed in the base substrate along the partition due line, using laser beams to form trenches and apply external forces to inhibit crack propagation to the bonding surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If external forces are applied to divide the semiconductor wafer, then the wafer can be divided into individual chips, but cracks may propagate to the bonding surface of the active layer, shortening chip lifespan

Engineering Contradiction:

Improvewafer division efficiencyVSAvoidchip lifespan

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a trench along the partition due line before applying external forces for wafer division. This trench, created by laser processing, serves as a pre-prepared separation path that guides crack propagation away from the bonding surface of the active layer, thus protecting the chip lifespan while enabling efficient wafer division.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary structure (the trench) between the external dividing forces and the bonding surface of the active layer. This trench acts as a mediator that intercepts and redirects the stress-induced cracks, preventing them from reaching the critical bonding surface while still allowing the wafer to be divided into individual chips.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If the wafer is divided along partition due lines, then individual device chips are obtained, but the bonding surface of the active layer is vulnerable to crack damage

Engineering Contradiction:

Improvechip fabrication processVSAvoidcrack damage to bonding surface

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by forming a trench along the partition due line before applying external forces for wafer division. This trench, created by laser processing, serves as a pre-prepared separation path that guides crack propagation away from the bonding surface of the active layer, thus protecting the chip lifespan while enabling efficient wafer division.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary structure (the trench) between the external dividing forces and the bonding surface of the active layer. This trench acts as a mediator that intercepts and redirects the stress-induced cracks, preventing them from reaching the critical bonding surface while still allowing the wafer to be divided into individual chips.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents crack extension to the bonding surface, thereby reducing damage to the active layer and extending the lifespan of semiconductor chips during the wafer division process.

Implementation Method 1

forming a trench along a partition due line (PDL) of a wafer by concentrating a first laser beam on a surface of the wafer and removing a portion of a protective layer and a portion of an active layer

Methodology Applied

Scientific EffectLaser ablation: Laser Ablation

Implementation Method 2

positioning, in the base substrate, a concentration point of a second laser beam having a wavelength transmitted through the wafer, and forming a modifier in the base substrate along the PDL

Methodology Applied

Scientific EffectLaser heating: Laser

Data Source

PatentUS20240355678A1Methods of dicing wafers having arrays of semiconductor chips therein and semiconductor chips formed thereby

Publication Date: 2024.10.24 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor chip includes an active layer on a top surface of an underlying base substrate. The active layer has: bonding surface therein that delineates an interface between a bottom active layer and a top active layer extending on the bottom active layer, and a chamfered edge that extends entirely through the top active layer to fully expose a sidewall thereof but only partially through the bottom active layer, such that the chamfered edge has a vertical height greater than a thickness of the top active layer but less than a combined thickness of the top and bottom active layers. A protective layer is also provided, which covers at least a portion of a top surface of the active layer. A vertical level of a bottom of the chamfered edge may be higher than a vertical level of the top surface of the base substrate.