Chip Diode Pad Positioning for P-N Junction Stress Relief

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Solution Overview

Problem

The existing semiconductor devices face issues where the p-n junction is damaged due to physical stress during mounting processes like ultrasonic bonding or flip-chip bonding, leading to fluctuations in characteristics and potential destruction of the p-n junction.

Innovation Solution

A chip diode design where the pad for electrical connection is positioned away from the p-n junction, with a semiconductor layer having a p-n junction, a first electrode connected to one side of the junction, and a second electrode connected to the other side, along with an insulating film acting as a cushion to reduce stress on the junction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the pad is positioned directly above the p-n junction for electrical connection, then the electrical connection is simplified and direct, but the p-n junction is damaged due to physical stress during mounting processes

Engineering Contradiction:
Improveelectrical connectionVSAvoidp-n junction integrity
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The chip structure is segmented into distinct functional zones: the pad region for electrical connection is spatially separated from the p-n junction region. This segmentation allows the pad to be positioned away from the junction, preventing stress transmission while maintaining separate optimization of each component's function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An insulating film is introduced as an intermediary layer between the pad and the p-n junction. This intermediary structure provides electrical isolation and mechanical cushioning, allowing the pad to receive external stress without transmitting it directly to the sensitive p-n junction below.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the pad is positioned away from the p-n junction, then the p-n junction is protected from physical stress, but the electrical connection path becomes longer and more complex

Engineering Contradiction:
Improvep-n junction integrityVSAvoidelectrical connection structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulating film serves multiple functions simultaneously: it provides electrical isolation between the pad and the semiconductor substrate, acts as a mechanical cushion to absorb stress, and serves as a structural support layer. This multi-functionality resolves the complexity issue by consolidating multiple required functions into a single element.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The insulating film automatically provides the necessary stress distribution and electrical isolation without requiring additional active components or complex control mechanisms. The structure itself serves its protective function through its inherent material properties and geometric configuration.

Inventive Principle:
Principle #25Self-service

3Strength

If ultrasonic bonding or flip-chip bonding is used for mounting, then the electrical connection strength is improved, but the physical stress destroys the p-n junction

Engineering Contradiction:
Improvebonding strengthVSAvoidp-n junction integrity
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The insulating film is pre-positioned between the pad and the p-n junction before the bonding process occurs. This beforehand cushioning structure is designed to absorb and distribute the mechanical stress that will be applied during ultrasonic or flip-chip bonding, preventing the stress from reaching the p-n junction while allowing strong bonding at the pad surface.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS10593814B2Semiconductor device having first and second electrode layers electrically disconnected from each other by a slit
Publication Date: 2020.03.17 ROHM CO LTD
  • US10593814B2 patent drawing
  • US10593814B2 patent drawing
  • US10593814B2 patent drawing

AI summary

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.