Chip Characteristic Distribution Modeling for Wafer Uniformity Prediction
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Solution Overview
Problem
Existing IC chip-assisted design techniques fail to account for non-uniform chip characteristics caused by process systematic defects such as rotational vibration and substrate tilting, leading to inconsistent chip performance across a wafer, which cannot be predicted at the circuit design stage.
Innovation Solution
A method and device that utilize a database and processor to generate and analyze chip characteristic distribution models based on sensor data from wafers, using machine learning algorithms like Generative Adversarial Networks to predict and correct chip characteristics, thereby improving design accuracy and production yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing IC chip-assisted design techniques are used, then the design process is simple, but chip characteristics uniformity deteriorates due to process systematic defects
Solution Approach 1:
The patent applies preliminary action by constructing chip characteristic distribution models before the actual circuit design process. The system pre-acquires process data from fabrication lines, builds predictive models of chip characteristic variations, and uses these models to guide design decisions in advance, thereby addressing uniformity issues before they manifest in final chip performance
Solution Approach 2:
The patent implements feedback by continuously acquiring actual process data from fabrication lines and using it to update and refine chip characteristic distribution models. The system compares predicted characteristics with actual measurements, feeds this information back into the model, and uses the refined model to improve subsequent design predictions, creating a closed-loop system that progressively improves accuracy
2Productivity
If process systematic defects are not considered, then the design stage is faster, but chip performance consistency deteriorates across the wafer
Solution Approach 1:
The patent applies copying by creating virtual representations of chip characteristic distributions through computational models. Instead of physically testing each chip location, the system generates digital copies of expected characteristic patterns based on process data, allowing designers to simulate and analyze performance consistency across the entire wafer virtual model before actual fabrication
Solution Approach 2:
The patent replaces physical trial-and-error fabrication with computational modeling and simulation. By substituting mechanical/fabrication processes with algorithm-based prediction systems that use process data to simulate chip characteristics, the system achieves faster design iteration while maintaining or improving performance consistency predictions
3Measurement precision
If chip characteristic distribution models are constructed using process data, then prediction accuracy improves, but data processing complexity increases
Solution Approach 1:
The patent applies extraction by selectively identifying and isolating the most critical process parameters that influence chip characteristics. Rather than processing all available process data equally, the system extracts key variables such as deposition thickness variations, etch rate differences, and annealing temperature gradients, focusing computational resources on the most impactful factors for prediction accuracy
Data Source
AI summary
A chip-assisted design device and a method for constructing a chip characteristic distribution model. The apparatus includes a database and a processor. The database has a first chip characteristic distribution image data generated based on a wafer fabrication process data of a current process, wherein the first chip characteristic distribution image data represents a gradient distribution of at least one chip characteristic in one of the wafers produced through current fabrication process. The processor is coupled to the database. A second chip characteristic image data generated based on the first chip characteristic image data is used as a reference data for predicting the future wafer fabrication process, and the reference data is provided to the current fabrication process to evaluate or correct the first chip characteristic image.