Multilevel Chip-to-Chip Driver with FIR Equalization for Noise Resilience
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Solution Overview
Problem
Current high-speed chip-to-chip communication systems face challenges in achieving high bandwidth, low latency, and low power consumption while maintaining resilience against noise and crosstalk, particularly in multi-chip systems where pin efficiency and power utilization are critical.
Innovation Solution
The implementation of a multilevel driver using vector signaling codes, such as the H4 and 5b6w codes, which transmit data over multiple wires with adjustable voltage levels, combined with multiphase processing and FIR filtering to optimize signal transmission and equalization, ensuring efficient data transfer across integrated circuit chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multilevel driver with vector signaling codes is used, then bandwidth and pin efficiency are improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by transitioning from traditional binary signaling to multilevel vector signaling codes (such as H4 and 5b6w codes). This changes the signaling parameter from 2 levels to 4 or more levels, enabling higher bandwidth and pin efficiency. The multilevel driver circuit implements this by using multiple current sources with different magnitudes to generate the additional signal levels, thereby resolving the contradiction between improved productivity and increased device complexity through deliberate parameter transformation.
2Productivity
If multilevel driver with vector signaling codes is used, then pin efficiency is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by transitioning from traditional binary signaling to multilevel vector signaling codes (such as H4 and 5b6w codes). This changes the signaling parameter from 2 levels to 4 or more levels, enabling higher bandwidth and pin efficiency. The multilevel driver circuit implements this by using multiple current sources with different magnitudes to generate the additional signal levels, thereby resolving the contradiction between improved productivity and increased device complexity through deliberate parameter transformation.
3Use of energy by moving object
If multilevel driver with vector signaling codes is used, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by transitioning from traditional binary signaling to multilevel vector signaling codes (such as H4 and 5b6w codes). This changes the signaling parameter from 2 levels to 4 or more levels, enabling higher bandwidth and pin efficiency. The multilevel driver circuit implements this by using multiple current sources with different magnitudes to generate the additional signal levels, thereby resolving the contradiction between improved productivity and increased device complexity through deliberate parameter transformation.
4Reliability
If multilevel driver with vector signaling codes is used, then noise and crosstalk resilience is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by transitioning from traditional binary signaling to multilevel vector signaling codes (such as H4 and 5b6w codes). This changes the signaling parameter from 2 levels to 4 or more levels, enabling higher bandwidth and pin efficiency. The multilevel driver circuit implements this by using multiple current sources with different magnitudes to generate the additional signal levels, thereby resolving the contradiction between improved productivity and increased device complexity through deliberate parameter transformation.
Data Source
AI summary
A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.


