Chip Edge Integrity Detection Structure for Dicing Damage
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Solution Overview
Problem
Die edge delamination or cracking during the dicing of semiconductor wafers leads to reliability issues and yield loss, especially with the introduction of low-k dielectrics in advanced technology nodes, which reduce mechanical strength and adhesion.
Innovation Solution
An edge integrity detection structure is integrated into the semiconductor product, comprising multiple interconnected planar electrically conductive layer structures that form a quasi-continuous electrically conductive wall. This structure is designed to detect edge damage by measuring changes in electrical resistance and is embedded in a seal ring to minimize extra chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low-k dielectric is introduced to reduce interconnect coupling capacitance, then coupling capacitance is reduced, but mechanical strength and adhesion decrease
Solution Approach 1:
The patent applies preliminary reinforcement to the die edges before the dicing process by forming a seal ring structure and edge assurance structure during the semiconductor manufacturing process. This preliminary action strengthens the edges against the inherent mechanical weakness introduced by low-k dielectric, enabling clean separation without delamination or cracking.
Solution Approach 2:
The invention uses composite material structures at the die edges, combining the low-k dielectric material with additional reinforcement materials (such as the seal ring and edge assurance structure) to create a composite edge region that maintains both the low capacitance benefit of low-k dielectric and the mechanical strength needed for clean dicing.
2Ease of manufacture
If traditional dicing methods are used, then manufacturing process is simple, but die edge delamination and cracking occur
Solution Approach 1:
The patent incorporates edge reinforcement structures (seal ring and edge assurance structure) during the semiconductor manufacturing process, before dicing occurs. This preliminary action ensures that when standard dicing methods are used, the edges are already strengthened and resistant to delamination and cracking, maintaining both manufacturing simplicity and edge integrity.
3Speed
If metal layer is heated during laser cutting, then cutting is achieved, but metal oxidizes and volume enlarges causing peeling and cracking
Solution Approach 1:
The patent replaces the laser-based thermal cutting method with a mechanical scribing and breaking method. The mechanical scribing creates a stress concentration line without significant heating, and the subsequent breaking separates the dies along this line, eliminating metal oxidization and the associated volume enlargement that causes peeling and cracking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The edge integrity detection structure effectively reduces the time required for monitoring devices for delamination and other defects, providing a reliable and efficient method for ensuring chip edge integrity, thus preventing device failures.
Implementation Method 1
This structure is designed to detect edge damage by measuring changes in electrical resistance
Data Source
AI summary
A semiconductor product, which comprises a semiconductor chip, an edge integrity detection structure extending along at least part of an edge of the semiconductor chip, and evaluation circuitry formed in and/or on the semiconductor chip, being electrically connected with the edge integrity detection structure, and being configured to evaluate an electric characteristic of the edge integrity detection structure to provide an evaluation signal indicative of a detected edge integrity status of the edge.