IC Chip Edge Profile Control for Low-Stress Die Singulation
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Solution Overview
Problem
The complexity of packaging integrated circuit (IC) chips increases with the scaling down of semiconductor devices, leading to thermal and mechanical stress-induced damages during the die-singulation process, resulting in delamination and void formation in the interconnect structures.
Innovation Solution
A three-stage die-singulation process is employed, involving a lithographic removal of stress buffer layers followed by laser grooving with reduced power density, combined with a tapered stress buffer layer structure to mitigate thermal and mechanical stress, thereby reducing thermal damages and enhancing IC chip reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional two-stage die-singulation process is used, then manufacturing simplicity is maintained, but thermal and mechanical stress-induced damages occur resulting in delamination and void formation
Solution Approach 1:
The die-singulation process is divided into three distinct stages: (1) lithographic removal of stress buffer layers from scribe lane areas, (2) laser grooving to form trenches through the wafer, and (3) dicing to separate individual dies. This segmentation allows each stage to address specific stress management requirements, preventing thermal and mechanical stress-induced damages while maintaining overall process reliability
Solution Approach 2:
The stress buffer layers are removed from scribe lane areas before the laser grooving and dicing operations. This preliminary action eliminates the stress concentration points that would otherwise cause delamination and void formation during subsequent high-stress operations, thereby preventing reliability issues before they occur
2Productivity
If laser grooving with high power density is used, then processing speed is improved, but thermal damages such as delamination and void formation increase
Solution Approach 1:
The stress buffer layers are extracted from the scribe lane areas before laser grooving. By removing these layers that would absorb excessive laser energy and generate thermal stress, the subsequent laser processing can be performed at higher power densities without causing delamination or void formation, thus maintaining both productivity and reducing thermal damages
Solution Approach 2:
The stress buffer layers are removed in advance to counteract the potential thermal damage that would occur during laser grooving. This preliminary anti-action prevents the harmful thermal effects by eliminating the source of stress concentration before the high-power laser processing begins
3Object-affected harmful factors
If stress buffer layers are removed from scribe lane areas, then thermal and mechanical stress is reduced, but manufacturing process complexity increases
Solution Approach 1:
The stress buffer layers are selectively removed only from the scribe lane areas where stress concentration occurs during die singulation, while preserving them in the active die areas where they provide structural support. This localized approach reduces thermal and mechanical stress in critical regions without unnecessarily complicating the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The three-stage process results in sharper edge profiles and significantly higher IC chip reliability, with a 10 times improvement compared to traditional two-stage methods, by minimizing delamination and void formation in the interconnect structures.
Implementation Method 1
a first stage of the die-singulation process can include removing portions of the stress buffer layer from scribe lane areas
Implementation Method 2
a second stage of the die-singulation process can include forming a trench in the wafer along the scribe lane by removing portions of the passivation layers, the interconnect structures, the device layer, and the wafer from the scribe lane areas
Implementation Method 3
a third stage of the die-singulation process can include dicing the wafer through the trench to separate individual dies from each other
Implementation Method 4
combined with a tapered stress buffer layer structure to mitigate thermal and mechanical stress
Data Source
AI summary
An integrated circuit chip package and a method of fabricating the same are disclosed. The method includes forming a device layer on a substrate with a first die and a second die, forming an interconnect structure on the device layer, depositing an insulating layer on the interconnect structure, forming first and second conductive pads on the interconnect structure, forming first and second conductive vias on the first and second conductive pads, respectively, patterning a polymer layer to form first and second buffer layers with tapered side profiles on the first and second conductive vias, respectively, forming a trench in the substrate and between the first and second buffer layers, and dicing the substrate through the trench to separate the first die from the second die. Portions of the first and second conductive pads extend over the insulating layer.