Semiconductor Chip Edge Region Testing for Block Failure Detection
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Solution Overview
Problem
Current burn-in tests for semiconductor chips are inefficient in identifying block failures, particularly in stacked memory chips, where edge region abnormalities such as corner missing or cracks can lead to prolonged electrical failure analysis and unclear root cause determination.
Innovation Solution
A testing method and system that involves performing read and write function tests on a preset number of memory cells in the edge region of a semiconductor chip, recording location information of abnormal cells, and judging whether the abnormalities are block-related based on this information, thereby shortening the time to confirm block abnormalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If electrical failure analysis is performed on failed chips to confirm block failure, then root cause determination is achieved, but testing period becomes excessively long
Solution Approach 1:
The patent applies preliminary action by conducting read and write function tests on memory cells in the edge region before the full burn-in test completes. This preliminary testing allows early detection of potential block failures, enabling the system to identify abnormal chips and determine root causes before the entire burn-in process finishes, thus significantly reducing the time required for failure analysis while maintaining accuracy.
2Reliability
If strict testing conditions are applied during burn-in test, then product quality detection is improved, but testing complexity and time increase
Solution Approach 1:
The patent applies segmentation by dividing the memory cell testing into specific regions (edge region versus interior region) and by separating the testing stages (preliminary read/write function test versus full burn-in test). This segmentation allows the system to apply strict testing conditions to critical edge regions where block failures are most likely to occur, while using less intensive testing for other regions, thereby maintaining high reliability detection without unnecessarily increasing overall testing complexity.
3Reliability
If full burn-in test is performed on all memory cells, then comprehensive quality detection is achieved, but testing time is excessively long
Solution Approach 1:
The patent applies the extraction principle by isolating and testing only the most critical memory cells located in the edge region, which are the most prone to block failures. By extracting these critical cells for preliminary testing, the system can identify potential block failures early without requiring all memory cells to undergo the complete burn-in test, thus achieving comprehensive quality detection for the most important areas while significantly reducing overall testing time.
Data Source
AI summary
The present invention relates to a testing method, a testing system, and a testing apparatus for a semiconductor chip. The method includes: acquiring a target chip; obtaining an abnormal chip after a test of read and write functions is performed separately on a preset number of memory cells in an edge region of the target chip; recording location information of individual memory cells with abnormal read and write functions on the abnormal chip; judging whether an abnormality of read and write functions of the abnormal chip is a block abnormality based on the location information; wherein the abnormal chip refers to the target chip including the memory cell with abnormal read and write functions.