IC Chip Edge Profile Singulation to Reduce Delamination
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Solution Overview
Problem
The complexity of packaging integrated circuit (IC) chips increases with the scaling down of semiconductor devices, leading to thermal and mechanical stress-induced damages during the die-singulation process, resulting in delamination and void formation in the interconnect structures.
Innovation Solution
A three-stage die-singulation process is employed, involving a lithographic removal of stress buffer layers followed by laser grooving with reduced power density, which is then followed by mechanical sawing, to form IC chips with sharper edge profiles and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional two-stage die-singulation process is used, then manufacturing simplicity is maintained, but thermal and mechanical stress-induced damages occur resulting in delamination and void formation
Solution Approach 1:
The die-singulation process is divided into three distinct stages: (1) lithographic removal of stress buffer layers from scribe lane areas, (2) laser grooving to form trenches, and (3) mechanical sawing to separate dies. This segmentation allows each stage to address specific stress and damage issues, improving reliability without requiring a complete process overhaul.
Solution Approach 2:
The stress buffer layers are removed in advance through lithographic processes before the laser grooving and mechanical sawing steps. This preliminary action prevents thermal and mechanical stress from accumulating during subsequent processing, thereby preventing delamination and void formation while maintaining a manageable process complexity.
2Productivity
If laser grooving with high power density is used, then cutting efficiency is improved, but thermal damages such as delamination and void formation increase
Solution Approach 1:
The stress buffer layers are removed through lithographic processes before laser grooving. This preliminary action eliminates the source of thermal stress that would otherwise cause delamination and void formation during high-power laser cutting, allowing efficient cutting without thermal damage.
Solution Approach 2:
The harmful stress buffer layers are extracted and removed from the scribe lane areas before the laser grooving process. This extraction eliminates the material that would absorb laser energy and generate thermal stress, enabling high-efficiency cutting without thermal damages.
3Object-affected harmful factors
If stress buffer layers are removed early, then thermal stress during laser grooving is reduced, but additional lithographic processing steps are required
Solution Approach 1:
The removal of stress buffer layers is segmented as a separate lithographic step performed before laser grooving. This segmentation allows precise control over where and how stress buffer layers are removed, reducing thermal stress during laser processing while adding only one discrete processing step to the overall flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process reduces thermal damages, enhancing IC chip reliability by up to 10 times compared to traditional two-stage methods, with lower power density lasers minimizing delamination and void formation.
Implementation Method 1
a first stage of the die-singulation process can include removing portions of the stress buffer layer from scribe lane areas using a lithographic process
Implementation Method 2
a second stage of the die-singulation process can include forming a trench in the wafer along the scribe lane by removing portions of the passivation layers, the interconnect structures, the device layer, and wafer from the scribe lane areas using a laser grooving process
Implementation Method 3
a second stage of the die-singulation process can include forming a trench in the wafer along the scribe lane by removing portions of the passivation layers, the interconnect structures, the device layer, and wafer from the scribe lane areas using a laser grooving process
Implementation Method 4
a third stage of the die-singulation process can include dicing the wafer through the trench to separate the dies from each other to form IC chips
Data Source
AI summary
An integrated circuit chip package and a method of fabricating the same are disclosed. The method includes forming a device layer on a substrate with a first die and a second die, forming an interconnect structure on the device layer, depositing an insulating layer on the interconnect structure, forming first and second conductive pads on the interconnect structure, forming first and second conductive vias on the first and second conductive pads, respectively, patterning a polymer layer to form first and second buffer layers with tapered side profiles on the first and second conductive vias, respectively, forming a trench in the substrate and between the first and second buffer layers, and dicing the substrate through the trench to separate the first die from the second die. Portions of the first and second conductive pads extend over the insulating layer.