Semiconductor Chip Edge Structure for Bonding Wire Reliability
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Solution Overview
Problem
There is a demand for increased performance and capacity of semiconductor packages with reduced size, and existing bonding wire connections are prone to defects due to warping and burrs, affecting the reliability and integration of semiconductor chips.
Innovation Solution
The semiconductor chip design includes a semiconductor substrate with protruding and recessed surfaces on its sides, a device layer with connection pads adjacent to these surfaces, and a peripheral protective layer with varying thicknesses to minimize contact with bonding wires, reducing defects and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the semiconductor package size is reduced to increase integration capacity, then the package area is decreased, but the bonding wire margins are reduced leading to increased defects
Solution Approach 1:
The invention transitions from a planar protection approach to a three-dimensional protective structure by forming protruding portions and recess surfaces on the semiconductor substrate side surface. This vertical dimensionality change allows the protective layer to extend over bonding wire paths without increasing the package footprint area, thus maintaining small package size while improving bonding wire reliability through enhanced spatial separation and protection.
Solution Approach 2:
The protective layer is applied selectively to specific regions where bonding wires pass over the semiconductor substrate side surface. Rather than uniformly protecting the entire substrate, the protruding portions and recess surfaces create localized protection zones precisely where bonding wire defects occur, optimizing the protection effectiveness while minimizing the impact on package size.
2Ease of manufacture
If conventional flat semiconductor substrate side surfaces are used, then the manufacturing process is simple, but bonding wires contact burrs and warping causing defects
Solution Approach 1:
The protective layer is formed on the semiconductor substrate side surface before the bonding wire attachment process. This preliminary protection prevents bonding wires from directly contacting burrs and warping on the substrate surface, eliminating defect sources before they can cause problems during wire bonding operations.
Solution Approach 2:
The protective layer acts as an intermediary between the bonding wires and the semiconductor substrate side surface. It provides a smooth intermediate surface that prevents direct contact between bonding wires and harmful surface features like burrs and warping, thereby improving bonding reliability without requiring changes to the substrate manufacturing process.
3Ease of manufacture
If the peripheral protective layer has uniform thickness, then the manufacturing process is simple, but it cannot effectively prevent current leakage and bonding wire defects
Solution Approach 1:
The protective layer thickness is varied locally to match the topography of the semiconductor substrate side surface. Thicker portions are formed over protruding portions and recess surfaces to ensure complete coverage and protection, while thinner portions exist in regions where the substrate surface is already favorable. This local thickness variation optimizes both protection effectiveness and current leakage prevention.
Solution Approach 2:
The protective layer conforms to the curved and irregular surfaces created by protruding portions and recess surfaces, forming a continuous protective coating that follows the three-dimensional topology. This curvature adaptation ensures uninterrupted protection along bonding wire paths and prevents current leakage by maintaining continuous electrical isolation.
Data Source
AI summary
A semiconductor chip includes a semiconductor substrate including a die region, and a peripheral region surrounding the die region; a device layer on the die region, the device layer including semiconductor devices and wiring layers; a peripheral protective layer surrounding the device layer on the peripheral region; and connection pads on an upper surface of the device layer and adjacent to one side of the upper surface of the device layer, wherein a side surface of the semiconductor substrate adjacent to the one side of the upper surface of the device layer includes protruding portions located at both corners and a recess surface indented into the die region between the protruding portions.