Chip Embedded Packaging Structure With Heat Dissipating Substrate
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Solution Overview
Problem
Existing IC packaging techniques face challenges in reducing the overall volume of packages, enhancing heat dissipation, and minimizing the distance between semiconductor chips and other components, which affects electrical performance and increases noise.
Innovation Solution
A chip embedded packaging structure is developed, featuring a heat dissipating substrate formed by two metal boards with through cavities, embedding semiconductor and capacitor chips, and integrating passive components with a build-up circuit layer and conductive vias for electrical connection, along with a passive component layer to form an MIM capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip chips and passive components are connected to the surface of the multi-layer circuit board, then the electrical connection distance becomes overly long, but the overall volume of the package cannot be reduced
Solution Approach 1:
The patent merges active chips and passive components into a single integrated substrate structure. The substrate contains through cavities that embed passive components while active chips are mounted on the surface, creating a compact unified package that reduces both volume and connection distance simultaneously.
Solution Approach 2:
The patent implements nesting by placing passive components inside through cavities within the substrate, effectively embedding them within the three-dimensional structure. This nested arrangement allows passive components to occupy internal space rather than surface area, reducing overall package volume while maintaining electrical performance.
2Reliability
If the distance between semiconductor chip and other components is reduced, then electrical performance improves, but heat dissipation capability may be affected
Solution Approach 1:
The patent applies local quality by creating distinct functional zones within the substrate: heat-generating active chips are positioned on the surface with direct thermal contact to the substrate, while passive components are embedded in through cavities. The substrate material itself is designed with thermal conductivity properties to locally manage heat flow from specific hot spots.
Solution Approach 2:
The substrate acts as an intermediary element that simultaneously provides electrical connection and thermal management. It mediates between the active chips and passive components by providing both electrical pathways through conductive vias and thermal pathways through its thermally conductive material structure.
3Area of stationary object
If multi-layer circuit boards with high wiring density are used, then space demand is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the circuit board into multiple functional layers with distinct purposes: signal transmission layers, power distribution layers, and thermal management layers. This segmentation allows each layer to be optimized independently for its specific function, simplifying the manufacturing process while achieving high wiring density in the signal layers without compromising thermal performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure increases heat dissipation efficiency, reduces noise, shortens wiring distances, and enhances electrical performance by integrating active and passive chips, achieving a compact, high-performance packaging solution.
Implementation Method 1
a heat dissipating substrate formed by two metal boards with through cavities, embedding semiconductor and capacitor chips
Implementation Method 2
integrating passive components with a build-up circuit layer and conductive vias for electrical connection
Data Source
AI summary
A chip embedded packaging structure includes a first metal board, a second metal board having at least a through cavity, in which the second metal board is disposed on the upper surface of the first metal board to form a heat dissipating substrate, at least a semiconductor chip and a capacitor chip embedded in the first metal board and embraced in the through cavity of the second metal board, a passive component layer disposed on part of the upper surface of the second metal board, and at least a build-up circuit layer covering the semiconductor chip, the capacitor chip, and the passive component layer and electrically connecting them through a plurality of conductive vias.