Semiconductor Chip Embedding With Plated Backside Connections

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Solution Overview

Problem

The challenge in microelectronic device manufacturing is achieving high integration and compact designs of semiconductor chips with diverse sizes and forms, requiring advanced chip integration technologies.

Innovation Solution

A method involving the embedding of semiconductor chips with plated back side connections and multiple layers of insulation and conductor layers, utilizing precise alignment and plating processes to create a core layer package that integrates chips of varying thicknesses and forms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple semiconductor chips of different sizes and forms are integrated, then device functionality and integration scale are improved, but manufacturing complexity and alignment precision requirements increase

Engineering Contradiction:

Improvechip integration capabilityVSAvoidmanufacturing process complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The manufacturing process is divided into distinct stages: substrate preparation, individual chip placement, insulation layer formation, conductor layer deposition, and plating operations. Each stage handles specific tasks independently, allowing complex multi-chip integration to be managed through sequential, modular operations rather than attempting all operations simultaneously.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Insulation layers are introduced as intermediary elements between semiconductor chips and conductor layers. These insulation layers provide a standardized interface that accommodates chips of varying sizes and forms, simplifying the integration process by decoupling the mechanical support function from the electrical connection function.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If chips of varying thicknesses are integrated, then design flexibility is improved, but warpage control and structural stability deteriorate

Engineering Contradiction:

Improvechip thickness variation capabilityVSAvoidpackage warpage

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The substrate serves as a counterweight structure that compensates for the varying thicknesses of individual chips. By providing a large-area, rigid base layer, the substrate distributes the mechanical stress from thickness variations across the entire package, preventing localized warpage and maintaining overall structural stability.

Inventive Principle:

Principle #8Anti-weight (Counterweight)

Solution Approach 2:

The package structure employs composite material layers including insulation materials, conductor materials, and plating materials. These composite layers are designed with different mechanical properties to compensate for warpage induced by chip thickness variations, creating a balanced structure that maintains stability despite component diversity.

Inventive Principle:

Principle #40Composite materials

3Reliability

If plated back side connections are used, then electrical connectivity is improved, but manufacturing process steps and time increase

Engineering Contradiction:

Improveelectrical connectivityVSAvoidmanufacturing cycle time

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The back side connections are prepared in advance through plating operations performed on the chip back surfaces before final assembly. This preliminary preparation ensures that electrical connection pathways are established early in the manufacturing process, allowing subsequent assembly steps to proceed without additional connection operations and reducing overall cycle time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Multiple manufacturing operations are merged into integrated process steps. For example, the plating process simultaneously forms both the electrical connection pathways and the structural reinforcement layers, eliminating the need for separate operations and reducing total manufacturing time while maintaining connection reliability.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables efficient integration of semiconductor chips with improved electrical connectivity and reduced warpage, facilitating higher integration and compactness in microelectronic devices.

Implementation Method 1

semiconductor chips with plated back side connections

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS12431450B2Device including semiconductor chips and method for producing such device

Publication Date: 2025.09.30 INFINEON TECHNOLOGIES AG

AI summary

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.