Programmable Chip Enable Switching Tree for Memory Bus Latency
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Solution Overview
Problem
In high-capacity storage applications, existing memory systems face challenges with heavy loading of the data bus due to multiple arrays of memory devices connected in parallel, leading to increased latency and reduced performance.
Innovation Solution
The implementation of a switching tree using multiplexers and demultiplexers to program a portion of the chip enable signals for a switching function, reducing the need for additional switching pins and pins, thereby reducing capacitance and latency by ensuring only the necessary data bus lines are connected to the active array during read/write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple arrays of memory devices are connected in parallel to support high capacity storage, then storage capacity is improved, but data bus loading increases causing increased latency and reduced performance
Solution Approach 1:
The patent segments the data bus into multiple independent data bus lines, each dedicated to a specific memory array. This segmentation allows each array to have its own dedicated data path to the host interface, eliminating the bottleneck of a shared data bus. When one array is accessed, only its dedicated data bus line is active, reducing the effective loading and latency compared to a shared bus where all arrays compete for the same data path.
2Quantity of substance
If multiple arrays of memory devices are connected in parallel to support high capacity storage, then storage capacity is improved, but data bus loading increases causing reduced performance
Solution Approach 1:
The data bus is segmented into multiple dedicated data bus lines, allowing simultaneous or independent data transfers to different memory arrays without contention. This increases overall system throughput by enabling parallel data operations across multiple arrays, as each array has guaranteed bandwidth through its dedicated data path rather than sharing a congested common bus.
Solution Approach 2:
The chip enable signals are given dual functionality: they serve both as traditional chip enable inputs for memory arrays and as control signals for the switching tree that routes data bus lines. This multi-functionality eliminates the need for separate switching control signals, reducing the number of pins required and simplifying the interface while maintaining high throughput capability.
3Adaptability or versatility
If additional switching pins are added to manage multiple arrays, then array selection capability is improved, but device complexity and pin count increase
Solution Approach 1:
The patent makes the chip enable signals multi-functional by using them both to enable memory arrays and to control the switching tree that routes data bus lines. This eliminates the need for additional dedicated switching control pins, as the same CE pins that enable arrays also serve as select inputs for the multiplexers in the switching tree, thereby maintaining high adaptability with reduced pin count and device complexity.
Solution Approach 2:
The patent merges the chip enable function and the array selection function into a single integrated control mechanism. The switching tree is controlled by the same chip enable signals that enable the arrays, combining what would traditionally be separate control functions into one unified system. This reduces the number of separate control pins needed while maintaining the ability to selectively access multiple arrays.
Data Source
AI summary
A memory module includes arrays of memory devices each having a data bus coupled to the data bus of a host memory channel by means of a switching tree. The switching tree is a tree of multiplexers that are controlled to couple the data lines of a single array to the data bus. In some embodiments, a first portion of the chip enable (CE) lines of a memory module are used to enable arrays of memory devices and a second portion are used to control the switching tree. The first portion may control a switching tree coupling the first portion to the enable inputs of the arrays.