Chip Encapsulation Layout for Lower Wire-Bond Arc Height
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Solution Overview
Problem
During the manufacturing of semiconductor chips, test keys can cause short circuits with pin pads due to their proximity, leading to defects and failures, and the resulting package thickness is increased by high arc heights to avoid these short circuits.
Innovation Solution
The test keys are positioned away from the leads, allowing for reduced arc heights and eliminating the risk of short circuits, thereby reducing the package thickness and failure rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test keys are disposed between multiple chips on the wafer, then process monitoring capability is improved, but short circuit risk during wire bonding increases
Solution Approach 1:
The patent relocates test keys from the traditional central region to the edge region of the chip, changing their spatial dimension and position. This dimensional relocation ensures test keys are outside the wire bonding arc area, eliminating short circuit risk while preserving process monitoring functionality.
Solution Approach 2:
The patent extracts test keys from the chip's functional area and places them in the edge region. This separation removes the harmful interaction between test keys and wire bonding leads, allowing process monitoring to continue without causing short circuits.
2Ease of manufacture
If test keys are located near the pin pad, then process testing is facilitated, but lead contact with test metal keys causes short circuit
Solution Approach 1:
The patent changes the spatial position of test keys from near the pin pad to the edge region of the chip. This dimensional relocation places test keys outside the wire bonding arc area, preventing lead contact and short circuit while maintaining process testing capability.
3Productivity
If conventional wire bonding is used with test keys present, then chip packaging is completed, but arc height is limited and chip thickness increases
Solution Approach 1:
The patent extracts test keys from the wire bonding arc area and places them in the edge region. This removal from the critical area allows the wire bonding arc to be lowered, reducing chip thickness while maintaining packaging functionality.
Solution Approach 2:
By relocating test keys to the edge region, the patent creates additional vertical space in the wire bonding area, enabling reduced arc height and thinner chip design without compromising packaging completion.
Data Source
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AI summary
A chip package structure and an electronic equipment may reduce probability of short circuit failure during chip packaging and improve chip reliability. The chip package structure includes: a chip, a substrate, and a lead; the chip is disposed above the substrate; wherein the chip includes a pin pad and a test metal key, and the lead is configured to electrically connect the pin pad and the substrate; the test metal key is disposed in an edge region of the chip that is not under the lead.