Chip Encapsulation Cavity Structure for Thin Multi-Chip Integration
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Solution Overview
Problem
Conventional chip encapsulation methods, such as wafer-level packaging and surface acoustic wave (SAW) filter encapsulation, face issues like high costs, complex processes, and instability, which hinder efficient multi-chip integration and signal transmission due to large encapsulation thickness and metal layer requirements.
Innovation Solution
A chip encapsulation structure and method involving a wafer with a groove, a first metal wire, a metal solder ball, and a plastic encapsulation film to form a closed cavity, along with an inductive structure connected through metal wires, allowing for face-down bonding and reduced encapsulation thickness, enabling efficient multi-chip integration and signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer-level packaging (WLP) is used for BAW chip encapsulation, then encapsulation protection is achieved, but the process becomes extremely complicated and expensive requiring two wafers to be bonded with through silicon via etching, Au—Au bonding
Solution Approach 1:
The patent extracts the chip from the complex WLP two-wafer bonding process and directly bonds it to a PCB substrate using simple solder balls. This eliminates the need for through silicon via etching, Au—Au bonding, and other complicated WLP processes, significantly simplifying the manufacturing process while maintaining encapsulation protection through a different approach.
Solution Approach 2:
The patent replaces the expensive and complex WLP process with a simpler, more cost-effective direct bonding approach using solder balls. This substitutes high-cost materials and processes (two-wafer bonding, Au—Au bonding) with lower-cost alternatives that achieve the same encapsulation and connection functions.
2Adaptability or versatility
If chips are horizontally distributed side by side and soldered to substrate through bump, then multi-chip interconnection is achieved, but large thickness of metal layer and dielectric layer results in signal transmission delay and large encapsulation thickness
Solution Approach 1:
The patent transitions from horizontal distribution of multiple chips side by side to a vertical stacking arrangement where chips are stacked above each other and connected through through-substrate vias. This dimensional change from 2D horizontal layout to 3D vertical stacking significantly reduces the signal transmission path length, thereby reducing signal transmission delay while achieving multi-chip interconnection.
3Reliability
If epoxy resin packing film covers top of SAW filter and PCB substrate, then cavity structure is formed, but epoxy resin may be thermally compressed into inside of metal bump with extremely high requirements for SAW thermal compression pressure
Solution Approach 1:
The patent replaces the problematic epoxy resin packing film with a metal cap for sealing the cavity structure. This substitution eliminates the issue of epoxy resin being thermally compressed into the metal bump during SAW thermal compression, as the metal cap provides a rigid, heat-resistant seal that does not suffer from the same compression and flow problems as epoxy resin.
4Ease of operation
If ceramic substrate is used for SAW filter bonding, then face-down bonding is achieved, but soldering cost becomes high and encapsulation size becomes large with unstability of device installation
Solution Approach 1:
The patent replaces the expensive ceramic substrate with a PCB substrate for face-down bonding of the SAW filter. This substitution significantly reduces soldering cost and encapsulation size while maintaining the face-down bonding capability. The PCB substrate provides adequate mechanical support and electrical connection without the high cost and large size associated with ceramic substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces encapsulation costs, simplifies the process, enhances chip stability, and achieves reliable cavity formation, improving mechanical resistance and air tightness while allowing for ultra-thin and efficient multi-chip integration with comprehensive impedance matching.
Implementation Method 1
a metal solder ball arranged on the first metal wire or on a metal pad of the chip, wherein the metal solder ball is configured to solder the metal pad of the chip to the first metal wire
Implementation Method 2
the first plastic encapsulation film covering the upper surface of the wafer, an upper surface of the chip and an upper surface of the first metal wire, and entering a gap between a periphery of a functional area of the chip and the first metal wire
Data Source
AI summary
A chip encapsulation structure, including: a wafer provided with a groove; a first metal wire arranged on surfaces of the groove and the wafer; a metal solder ball arranged on the first metal wire or on a metal pad of the chip, and is configured to solder the metal pad of the chip to the first metal wire; a first plastic encapsulation film covering upper surfaces of the wafer, the chip and the first metal wire, and entering a gap between a periphery of a functional area of the chip and the first metal wire, so as to form a closed cavity among the wafer, the groove and the chip; an inductive structure arranged on an upper surface of the first plastic encapsulation film and/or a lower surface of the wafer, and connected to the chip through the first metal wire; and a pad arranged on the inductive structure.