Chip Feature Activation via Power-Pin Voltage Pattern Detection
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Solution Overview
Problem
Existing chip communication protocols are limited to specific settings, making it difficult to access all chips through a common protocol, as various protocols are supported by different systems, and there is a need for a universal communication method.
Innovation Solution
A method where a chip with at least two power pins measures voltage values, detects sync signals interleaved with these values, and activates a feature if the data sequence matches a predefined pattern, allowing for the use of a generic communication protocol or mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple specific communication protocols are supported by different systems, then chips can communicate with their respective systems, but it becomes difficult or impossible to access all chips through a common communication protocol
Solution Approach 1:
The patent applies universality by creating a standardized activation sequence protocol that can be used across all chip types regardless of their specific communication protocols (I2C, SPI, USB, UART, etc.). The activation sequence using voltage levels and sync signals provides a universal interface that works with diverse chip architectures, eliminating the need for protocol-specific activation methods.
Solution Approach 2:
The patent uses parameter changes by defining specific voltage level sequences and timing parameters that can be transmitted through existing communication interfaces. By varying voltage levels (high/low states) and timing (sync signal positions), the system encodes activation information using parameters that are inherent to digital communication, allowing protocol-agnostic feature activation.
2Adaptability or versatility
If a new communication protocol is created to apply to all kinds of chip, then universal access is enabled, but the complexity of implementing and detecting the protocol increases
Solution Approach 1:
The patent employs periodic action through the use of sync signals that appear at regular, predetermined positions within the activation sequence. These sync signals serve as periodic markers that help the chip identify and synchronize with the activation protocol, making detection easier by providing recognizable reference points in the voltage sequence.
Solution Approach 2:
The patent uses voltage levels and sync signals as intermediaries between the external system and the chip's internal features. Rather than requiring direct protocol-specific commands, the activation sequence uses these intermediary voltage patterns to convey feature activation information in a way that can be detected and processed by diverse chip types.
3Reliability
If feature activation requires matching predefined patterns, then security and precision are improved, but the complexity of the activation process increases
Solution Approach 1:
The patent applies preliminary action by pre-defining the activation sequences and patterns during chip design and manufacturing. The expected voltage sequences and sync signal positions are established in advance, allowing the chip to have built-in knowledge of what constitutes a valid activation command. This eliminates the need for complex real-time decision-making during activation.
Solution Approach 2:
The patent uses feedback by having the chip detect and verify the received voltage sequence against predefined patterns. The sync signals serve as feedback markers that confirm proper synchronization, and the pattern-matching process provides feedback on whether the activation sequence was correctly received and interpreted, ensuring reliable feature activation.
Data Source
AI summary
Method for activating a feature of a chip having an interface comprising at least two power pins. The method comprises the following steps: the chip measures a series of voltage values between said power pins, the chip detects a series of sync signals different from clock signals, said sync signals being interleaved with said voltage values, the chip identifies a data sequence from said series of voltage values, and the chip activates the feature only if the data sequence matches a predefined pattern.