Chip-on-Film Bump Layout for Lower Gold Use in Probe Testing
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Solution Overview
Problem
Existing semiconductor chip probe test processes are costly due to the use of gold bumps, and there is a need to reduce the size of these bumps without compromising the functionality and reliability of the chip.
Innovation Solution
The semiconductor chip design includes larger first bumps for chip probe testing and smaller second bumps for non-testing purposes, maintaining the same height and width dimensions but reducing the overall size of the bumps, primarily made of gold, thereby lowering production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of all bumps is reduced to lower production costs, then the material cost decreases, but the chip probe test functionality may be compromised
Solution Approach 1:
The patent applies different bump sizes to different functional groups: larger bumps (first bumps) are used for pads requiring chip probe testing to maintain test functionality, while smaller bumps (second bumps) are used for pads not requiring testing to reduce material cost. This local differentiation resolves the contradiction by preserving reliability where needed while reducing quantity of gold material where testing is not required.
2Ease of manufacture
If the size of bumps is reduced, then production costs decrease, but the electrical connectivity and functionality may be affected
Solution Approach 1:
The invention implements local quality differentiation by assigning larger bump sizes to first pads that require electrical testing and smaller bump sizes to second pads that do not require testing. This ensures that electrical connectivity is maintained at adequate levels for testing purposes while reducing overall gold material usage and production costs.
Solution Approach 2:
The patent segments the bump population into two distinct groups based on functional requirements: first bumps for test-critical pads and second bumps for non-test pads. This segmentation allows optimized performance for each group, maintaining reliability where needed while reducing costs overall.
Data Source
AI summary
A semiconductor chip including a plurality of first pads, a plurality of second pads, a plurality of first bumps, and a plurality of second bumps is provided. The first pads and the second pads are arranged along a direction of a long side of an active surface of the semiconductor chip. The first bumps are disposed on the first pads, and configured for a chip probe test. The second bumps are disposed on the second pads, and not for the chip probe test. A size of the first bump is larger than a size of the second bump.