Chip-Film PCB Embedding for Vertical Chip Interconnects

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Solution Overview

Problem

Current microelectronic manufacturing techniques face challenges in miniaturization, integration density, and cost-effectiveness due to complex processes and fragility of semiconductor chips, especially in three-dimensional integration and printed circuit board integration, where small contact pads and high yield are difficult to achieve with existing methods.

Innovation Solution

A method involving a chip-film module with a semiconductor chip integrated into a thin film substrate, where the chip-film module is embedded into a printed circuit board, expanding contact pad sizes and distances to match standard PCB production geometries, enabling vertical electrical or optical connections and simplifying manufacturing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Extent of automation

If conventional wafer-to-wafer integration techniques are used, then three-dimensional integration is achieved, but manufacturing complexity and cost increase due to elaborate process sequences and special semiconductor factory requirements

Engineering Contradiction:

Improveintegration densityVSAvoidmanufacturing process complexity

Core Design Contradiction:

Extent of automationVSDevice complexity

Solution Approach 1:

The patent introduces a film substrate as an intermediary carrier that simplifies the integration process. Instead of directly integrating wafers using complex semiconductor factory processes, the invention uses a film substrate as a mediator to mount semiconductor chips and establish electrical connections, thereby reducing manufacturing complexity while maintaining integration density

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention extracts the semiconductor chips from the wafer substrate and mounts them individually onto the film substrate. This separation allows for selective mounting of only functional chips, eliminating the need to process entire wafers and reducing manufacturing complexity associated with wafer-level integration

Inventive Principle:

Principle #2Taking out (Extraction)

2Ease of manufacture

If glass interposers are used instead of silicon substrates, then insulation requirements are omitted, but the thin glass wafers are very prone to breakage

Engineering Contradiction:

Improveinsulation requirementVSAvoidsubstrate fragility

Core Design Contradiction:

Ease of manufactureVSStrength

Solution Approach 1:

The patent replaces rigid glass or silicon wafers with a flexible film substrate. This thin film structure eliminates the fragility issue of thin glass wafers while providing sufficient mechanical support for mounting semiconductor chips and establishing electrical connections

Inventive Principle:

Principle #30Flexible shells and thin films

Solution Approach 2:

The film substrate serves as a disposable or temporary carrier that simplifies the manufacturing process. After the chips are mounted and connected, the film substrate can be removed or remains as a flexible interconnection layer, avoiding the need for durable but fragile glass or silicon substrates

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Productivity

If chip components are contacted on a wafer, then all chip components can be processed, but yield is lost due to processing of non-functional components

Engineering Contradiction:

Improveprocessing throughputVSAvoidyield loss

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent performs preliminary testing and selection of semiconductor chips before mounting them onto the film substrate. This preliminary action ensures that only functional chips are processed and integrated, eliminating yield loss from processing non-functional components while maintaining productivity through selective mounting

Inventive Principle:

Principle #10Preliminary action

4Ease of operation

If small contact pads on semiconductor chips are directly contacted using PCB structuring techniques, then wiring can be established, but the contact pad size is too small for reliable contact and wiring with high yield

Engineering Contradiction:

Improvewiring capabilityVSAvoidcontact pad size

Core Design Contradiction:

Ease of operationVSManufacturing precision

Solution Approach 1:

The patent transitions from planar two-dimensional contact pad geometry to three-dimensional vertical connections. By using vertical vias and elevated contact structures on the film substrate, the invention effectively increases the contact area and makes wiring more reliable without requiring larger chip contact pads

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11901285B2Microelectronic arrangement and method for manufacturing the same

Publication Date: 2024.02.13 FRAUNHOFER GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG EV

AI summary

Embodiments provide a method for manufacturing a microelectronic arrangement. The method includes a step of providing a chip-film module with a semiconductor chip and a film substrate having arranged thereon the semiconductor chip, wherein the chip-film module includes at least one coupling element spaced apart from the semiconductor chip and electrically coupled to at least one terminal of the semiconductor chip. Furthermore, the method includes a step of embedding the chip-film module into a printed circuit board, wherein, in embedding the chip-film module into the printed circuit board, the at least one coupling element of the chip-film module is coupled vertically [e.g. in the vertical direction [e.g. in relation to the printed circuit board]] [e.g. perpendicular to a surface of the printed circuit board] to at least one coupling counter element of the printed circuit board.