Chip-on-Film Redistribution Layout for Void-Free Fine-Pitch Packaging
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Solution Overview
Problem
Current chip-on-film packaging technologies face challenges in achieving high integration density and reliable electrical characteristics, particularly due to void formation in under-fill layers and potential deterioration of transistor electric characteristics when lead lines are extended to the center region of the chip.
Innovation Solution
The implementation of a redistribution pattern on the bottom surface of the semiconductor chip, which allows lead lines to be spaced apart from the center region, preventing void formation and improving reliability, while also arranging connection terminals in a zigzag shape to reduce pitch and increase design freedom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lead lines are extended to the center region of the chip to increase integration density, then the integration density is improved, but void formation occurs in the under-fill layer and transistor electric characteristics deteriorate
Solution Approach 1:
The patent divides the connection structure into multiple segments: redistribution patterns on the chip bottom surface, connection terminals on the film substrate, and lead lines on the film substrate. This segmentation allows the lead lines to be positioned away from the chip center region while maintaining electrical connectivity, thus preventing void formation and transistor characteristic deterioration while achieving high integration density through optimized spatial arrangement.
Solution Approach 2:
The patent introduces redistribution patterns as an intermediary structure between the chip pads and the lead lines. These redistribution patterns are formed on the bottom surface of the chip and connect to chip pads, while connection terminals on the film substrate connect to the lead lines. This intermediary structure enables the lead lines to be positioned in the edge region rather than extending to the chip center, resolving the contradiction between integration density and reliability.
2Volume of moving object
If connection terminals are arranged in a zigzag shape to reduce pitch, then the package size is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent transitions from a linear arrangement of connection terminals to a zigzag (two-dimensional) arrangement on the film substrate surface. This dimensional change allows the terminals to be packed more densely within the same area, reducing the overall package footprint. The zigzag pattern optimizes space utilization while maintaining manufacturability through standard photolithography and metal deposition processes.
Data Source
AI summary
A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.