Retention-Based Chip Fingerprinting With Dynamic Key Guard-Banding
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Solution Overview
Problem
Existing chip identification methods face challenges in generating a reliable and unique intrinsic ID that is stable over time, secure from copying, and cost-effective, with a risk of misidentification and system overhead due to process variations and potential instability of generated bits.
Innovation Solution
A method using dynamic and static random access memory arrays to generate intrinsic retention-based ID strings, employing challenge-response pairs and built-in-self-test engines to create tamper-proof, low-cost, high-security chip identification with minimal additional circuitry, leveraging manufacturing process variations for unique parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the vector length is increased to reduce the chance of having the same ID for multiple chips, then the uniqueness of chip ID is improved, but the system overhead to manage long vector patterns increases
Solution Approach 1:
The patent extracts only the essential retention characteristics from the memory array to form the chip ID, rather than using the entire memory response. By selecting specific retention-based features that uniquely identify the chip, the system achieves high uniqueness with a compact ID vector, thereby reducing system overhead while maintaining reliability.
Solution Approach 2:
The patent changes the parameter used for ID generation from general memory content to specific retention characteristics under controlled conditions. By adjusting retention time and reading conditions, the system generates stable and unique chip IDs with optimized vector length, balancing uniqueness requirements with system complexity management.
2Reliability
If retention time is extended to ensure ID stability, then the reliability of chip identification is improved, but the risk of data leakage increases
Solution Approach 1:
The patent performs preliminary writing of test patterns to the memory array before generating the chip ID. By pre-configuring the memory with known patterns and then reading the retention characteristics, the system ensures stable ID generation without requiring extended retention times that would increase security risks. The preliminary action establishes a controlled baseline for reliable identification.
Solution Approach 2:
The patent converts the natural retention characteristic, which could potentially lead to data leakage if extended, into a beneficial feature by using it to generate unique chip IDs. By utilizing the inherent retention behavior under controlled, limited time conditions, the system achieves both ID stability and security, turning a potential vulnerability into a reliable identification mechanism.
3Reliability
If additional circuitry is added to improve ID generation accuracy, then the reliability of identification is improved, but the cost and area overhead increase
Solution Approach 1:
The patent makes the memory array serve multiple functions: it acts as both the primary storage element and the source for generating unique chip IDs. By utilizing the inherent physical characteristics of the existing memory cells without adding dedicated ID generation circuitry, the system achieves high identification accuracy while minimizing additional cost and area overhead.
Solution Approach 2:
The patent enables the memory array to self-generate the chip ID by exploiting its own retention characteristics. The memory cells naturally exhibit unique retention behaviors due to manufacturing variations, and the system simply reads these characteristics to generate the ID. This self-service approach eliminates the need for additional complex circuitry, reducing both cost and area overhead while maintaining high reliability.
Data Source
AI summary
A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.