Chip-First Layered Packaging With Copper TDVs for Reliable Interconnects
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Solution Overview
Problem
Conventional interposer technology in microelectronic packaging relies on solder-based interconnects, which have reliability issues such as void formation, signal propagation delays, and thermo-mechanical fatigue, leading to reduced power delivery and signal integrity, and increased costs due to the need for multiple interconnects.
Innovation Solution
A chip-first advanced packaging technology using copper pillar structures as through-dielectric vias (TDVs) and microbumps for direct connections between IC dies and a package substrate, reducing the complexity and number of interconnects while enabling multiple layers of disaggregated IC dies with improved power delivery and signal connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder-based interconnects are used in conventional interposer technology, then electrical connectivity between IC dies and package substrate is achieved, but reliability deteriorates due to void formation, signal propagation delays, and thermo-mechanical fatigue
Solution Approach 1:
The patent extracts and removes the solder-based interconnect layer from the packaging structure, replacing it with direct copper pillar-to-copper pillar bonding. This eliminates the harmful solder material while maintaining electrical connectivity, thereby improving reliability by removing the source of void formation and thermo-mechanical fatigue.
Solution Approach 2:
The patent changes the material parameter from solder to copper, and the structural parameter from multi-layer interconnect to direct bonding. This parameter change transforms the interconnect system from one prone to reliability issues to one with superior thermal and electrical performance.
2Power
If multiple solder-based interconnects are used to ensure connectivity, then electrical pathways are established, but power delivery deteriorates due to increased resistance and signal loss
Solution Approach 1:
The patent merges the previously separate interconnect layers into a single direct bonding interface. By combining the copper pillar structures and eliminating the intermediate solder layers, the system achieves lower resistance and improved power delivery while enhancing signal integrity through reduced propagation delays.
Solution Approach 2:
The patent employs copper-copper direct bonding instead of solder-based composites. This material substitution creates a homogenous, high-conductivity pathway that superiorly conducts power and signals compared to the heterogeneous solder-based structures.
3Ease of manufacture
If conventional solder-based interconnect technology is used, then IC packaging is achieved, but manufacturing cost increases due to the need for multiple interconnect layers and associated processing
Solution Approach 1:
The patent extracts and eliminates the intermediate solder interconnect layers, reducing the total number of interconnect structures from multiple layers to a single direct bonding interface. This simplification directly reduces manufacturing process complexity and associated costs.
Solution Approach 2:
Instead of building up multiple interconnect layers from bottom to top, the patent inverts the approach by using direct bonding between copper pillars, effectively reducing the structure from many layers to one, thereby simplifying the manufacturing process.
Data Source
AI summary
Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die having first bond-pads on a first surface; an organic dielectric material in contact with the first surface; second bond-pads on a second surface of the organic dielectric material opposite to the first surface; through-dielectric vias (TDVs) in the dielectric material between the first bond-pads and the second bond-pads, wherein the TDVs are in direct contact with the first bond-pads and the second bond-pads; a second IC die embedded in the organic dielectric material and coupled to the first bond-pads by first interconnects; and a package substrate coupled to the second bond-pads by second interconnects.