Chip Floorplan Activity Estimation for Power Distribution
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Solution Overview
Problem
Current chip design methods lack an effective way to associate simulation information with localized power consumption within the chip floorplan, visualize power distribution, and optimize placement to improve power consumption distribution.
Innovation Solution
A system and method to estimate and visualize localized activity distribution within a chip floorplan by calculating activity based on unit location and activity levels, using simulation data or calculated activity, and optimizing chip design through iterative processes or software execution on computing devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simulation information is used to estimate power consumption, then power consumption data can be obtained, but it is difficult to associate simulation information with localized power consumption within the chip floorplan
Solution Approach 1:
The chip floorplan is divided into discrete regions corresponding to logical units, allowing simulation information to be segmented and associated with specific localized areas. Each logical unit's power consumption is calculated independently based on its activity level, enabling precise localized measurement without complex global association.
Solution Approach 2:
An intermediary data structure is introduced to map simulation information to floorplan locations. This intermediary layer translates abstract simulation data into spatially-resolved power consumption metrics, simplifying the association process while maintaining measurement precision.
2Measurement precision
If activity distribution is calculated for all locations in the floorplan, then localized power consumption can be estimated, but calculation complexity increases
Solution Approach 1:
Instead of calculating activity distribution uniformly across the entire floorplan, the method focuses calculations on specific logical units and their immediate surrounding regions. Each logical unit's activity is calculated based on its own activity level and location, reducing overall calculation complexity while maintaining precision where it matters most.
3Loss of energy
If iterative optimization process is used to optimize chip design, then power consumption distribution can be improved, but design time increases
Solution Approach 1:
The system performs preliminary activity distribution calculations during the design phase, identifying potential power consumption issues before finalization. By calculating and visualizing activity distributions in advance, designers can make informed placement decisions that reduce power consumption without requiring extensive iterative optimization, thus reducing design time.
4Power
If maximum instantaneous power consumption is minimized through optimization, then power distribution is improved, but placement flexibility is reduced
Solution Approach 1:
The optimization system dynamically adjusts logical unit placements based on activity distribution calculations. Rather than fixing placements early, the system continuously evaluates and adjusts positions to minimize maximum instantaneous power consumption while maintaining placement flexibility throughout the design process. This dynamic approach allows adaptation to different power constraints without sacrificing versatility.
Data Source
AI summary
Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan.