Chip Design Flow Slicing for ML-Guided QoR and Runtime Tradeoffs
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Solution Overview
Problem
The challenge in integrated circuit (IC) design is the enormous and impractical total design search space, which requires long execution times and degrades quality of result (QoR) due to inefficient use of machine learning (ML) reward functions, especially in detail routing, leading to increased runtime and suboptimal final designs.
Innovation Solution
The design flow is divided into sub-steps using flow-slicing, allowing for faster, parallel execution of sub-steps with ML optimization, utilizing intermediate rewards to select top diverse designs and dynamically chain sub-steps for efficient optimization, reducing computational requirements and improving QoR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the total design search space is searched exhaustively, then the quality of result (QoR) is improved, but the runtime becomes impractically long
Solution Approach 1:
The patent divides the design flow into multiple sub-steps (flow-slicing), where each sub-step processes a portion of the design space. This segmentation allows the system to explore diverse intermediate designs through different sub-steps rather than exhaustively searching the entire design space sequentially, thereby improving QoR while reducing runtime.
Solution Approach 2:
The patent uses machine learning models to predict and select promising intermediate designs before complete execution of the full design flow. By performing preliminary evaluation and selection of intermediate designs that are likely to lead to high-QoR final designs, the system avoids exhaustive search while maintaining quality.
2Manufacturing precision
If machine learning reward functions are used to optimize design, then the quality of result (QoR) is improved, but the runtime increases due to inefficient evaluation
Solution Approach 1:
The patent segments the design flow into sub-steps, allowing ML reward functions to evaluate intermediate designs at multiple stages rather than only at the final stage. This enables earlier feedback and more efficient use of computational resources, improving productivity while maintaining QoR improvement.
Solution Approach 2:
The patent applies ML optimization partially through selected sub-steps rather than uniformly across the entire design flow. By identifying and applying ML optimization only where it provides the most benefit, the system improves QoR while minimizing the runtime overhead associated with ML evaluation.
3Manufacturing precision
If the design flow is executed completely for each input combination, then the quality of result (QoR) is improved, but the computational requirements increase
Solution Approach 1:
The patent divides the design flow into executable sub-steps that can be independently evaluated. This allows the system to compute intermediate results for multiple input combinations in parallel and use ML to select promising candidates for further processing, reducing overall computational requirements while maintaining QoR.
Solution Approach 2:
The patent uses machine learning models to create surrogate representations of the design evaluation process. Instead of executing the complete design flow for every input combination, the ML models predict outcomes based on patterns learned from a subset of executions, significantly reducing computational requirements while preserving QoR improvement.
Data Source
AI summary
A method includes generating a plurality of intermediate designs for a chip by executing a first sub-step based on a first plurality of inputs, adding at least one intermediate design of the plurality of intermediate designs to a second plurality of inputs, generating a plurality of final designs by executing a second sub-step of the step of the design flow based on the second plurality of inputs, and selecting using a machine learning model a final design from the plurality of final designs. The first sub-step is a sub-step of a step of a design flow and the first plurality of inputs corresponds to input parameters associated with the first sub-step.