Chip Computing Function Templates for Dynamic AI Workloads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional AI chips face challenges in efficiently adapting to various application scenarios and operation scales due to complex configurable parameters and lengthy development cycles, leading to low software development efficiency and suboptimal performance.
Innovation Solution
A method for generating a chip-based computing function using candidate computing function templates with configurable parameters, dynamically configured through machine learning and just-in-time compilation, to adapt to different application scenarios and operation scales.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional processors are used for deep learning, then general-purpose computing is maintained, but performance and power consumption requirements cannot be met
Solution Approach 1:
The patent combines multiple computing function templates (matrix multiplication, convolution, element-wise operations) into a single unified chip computing function template, allowing the chip to perform various deep learning operations through software configuration rather than requiring separate hardware for each operation, thus improving power efficiency while maintaining high performance
Solution Approach 2:
The patent implements dynamic configuration of computing function templates through machine learning and just-in-time compilation, allowing the chip to adapt its computing functions to different application scenarios and operation scales, optimizing performance and power consumption based on actual workload requirements
2Adaptability or versatility
If complex configurable parameters are used in AI chips, then adaptability to different application scenarios is improved, but software development efficiency decreases
Solution Approach 1:
The patent employs machine learning algorithms to automatically select and configure optimal computing function templates based on input parameters, eliminating the need for manual configuration by developers. The system serves itself by autonomously determining the best configuration for given application scenarios, thus maintaining high adaptability while improving software development efficiency
Solution Approach 2:
The patent introduces just-in-time compilation as an intermediary layer between high-level programming languages and chip hardware, automatically translating and configuring computing functions at runtime. This mediator handles the complexity of parameter configuration, allowing developers to write simple high-level code while the system manages the complex hardware configuration automatically
3Ease of operation
If manual configuration of chip parameters is used, then control over computing functions is maintained, but development cycles become lengthy
Solution Approach 1:
The patent pre-defines multiple computing function templates (matrix multiplication, convolution, element-wise operations) with various configurations before runtime. During execution, the system simply selects and activates the appropriate pre-configured template based on the application requirements, eliminating the need for time-consuming manual configuration while maintaining full control over computing functions
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
Embodiments of the present disclosure provide a method and apparatus for generating a chip-based computing function, a device, and a storage medium. The method includes: acquiring an input parameter value associated with a computing function supported by a chip; determining, based on the input parameter value, at least one candidate computing function template corresponding to the computing function, the candidate computing function template having a configurable parameter associated with performance of the candidate computing function template, and the configurable parameter having at least one candidate value; and determining, according to the input parameter value and candidate values of the configurable parameter of the candidate computing function template, a target computing function template and a target value of a configurable parameter of the target computing function template to implement the chip-based computing function. With the method, the design of chips can be dynamically adapted to different application scenarios/operation scales, and configurable parameters are dynamically configured, thereby greatly simplifying the difficulty in manually implementing computing function templates, and improving the efficiency of chip design, especially chip software development.