Semiconductor Package Layout With Low Chip-to-Gap Ratio Cooling
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving smaller volume and thinner size without compromising structural strength and heat dissipation efficiency, leading to uneven heating and performance instability of chips.
Innovation Solution
A semiconductor packaging structure with a controlled ratio of chip thickness to substrate distance of less than 0.5, combined with a heat dissipation structure on the chip, ensures stable chip performance and efficient heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the thickness of the logic chip is reduced to achieve smaller volume and thinner size, then the volume and thickness of the packaging structure are reduced, but the structural strength of the logic chip is reduced and the reliability of the packaging structure is affected
Solution Approach 1:
The patent applies nested doll principle by placing the logic chip between the first substrate and the second substrate in a vertical stacking configuration. The first chip is nested within the space defined by the two substrates, with the first substrate providing support from below and the second substrate providing support from above. This nested arrangement allows the chip to be protected and supported by surrounding structures, maintaining structural strength while achieving compact volume.
2Volume of moving object
If the thickness of the logic chip is reduced to achieve smaller volume and thinner size, then the volume and thickness of the packaging structure are reduced, but the uniformity of heat distribution on the chip is affected and operation performance is reduced
Solution Approach 1:
The patent introduces a heat dissipation structure as an intermediary element between the logic chip and the surrounding environment. This heat dissipation structure acts as a mediator to transfer heat uniformly across the chip surface, preventing localized overheating. The structure includes thermal conduction paths that distribute heat from high-density computation areas to cooler regions, maintaining thermal uniformity even when the chip thickness is reduced.
3Length of stationary object
If the distance between the first substrate and the second substrate is reduced to achieve thinner size, then the thickness of the packaging structure is reduced, but the space for heat dissipation is reduced and heat dissipation efficiency is affected
Solution Approach 1:
The patent transitions heat dissipation from a primarily vertical (one-dimensional) approach to a multi-dimensional approach. The heat dissipation structure extends in multiple directions including lateral expansion within the available space between substrates, and utilizes the substrate surfaces as heat sinks. This dimensional change allows efficient heat dissipation even when the vertical distance between substrates is reduced, as heat can escape through multiple pathways including the chip edges and substrate interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Maintains structural stability and performance of chips while reducing volume and thickness, improving heat dissipation efficiency, and preventing temperature thresholds.
Implementation Method 1
a heat dissipation structure disposed on the first chip
Data Source
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AI summary
A semiconductor packaging structure includes: a first packaging body (100) and a second packaging body (200). The first packaging body (100) includes a first substrate (110) and a first chip (120), and the first chip (120) is located on the first substrate (110). The second packaging body (200) is coupled to the first packaging body (100) and includes a second substrate (210), the first chip (120) is located between the first substrate (110) and the second substrate (210). A ratio of a thickness T1 of the first chip (120) to a distance D1 between the first substrate (110) and the second substrate (210) is less than 0.5.