On-Chip Power-Glitch Detection with Internal Self-Testing
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Solution Overview
Problem
Existing systems-on-chip (SoC) designs lack effective methods to detect and counter power-glitch attacks, which are sophisticated hacking techniques that compromise chip security.
Innovation Solution
A chip design incorporating a processor, glitch detector, and self-testing circuit with a glitch generator and controller, enabling internal power-glitch detection and self-testing without external test pads, using a phase-locked loop for sharp glitch signals and multiplexers for mode switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power-glitch detection is implemented on chip, then chip security against power-glitch attacks is improved, but device complexity increases due to additional glitch detector and self-testing circuit components
Solution Approach 1:
The glitch detector and self-testing circuit are integrated within the chip architecture, merging security functions with existing processor and power management structures. This consolidation improves chip security while minimizing the increase in device complexity by sharing resources and avoiding separate external testing infrastructure.
Solution Approach 2:
The self-testing circuit enables the glitch detector to automatically test and verify its own functionality through internal glitch signal generation and detection. This self-service capability ensures reliable power-glitch detection without requiring external testing equipment, thereby improving security while keeping the device complexity manageable through autonomous operation.
2Reliability
If self-testing circuit is added for glitch verification, then detection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The self-testing circuit is divided into functional modules including glitch signal generation, glitch injection, and verification components. This segmentation allows for modular manufacturing and testing, improving detection reliability while facilitating easier fabrication through standardized modular processes.
Solution Approach 2:
The self-testing circuit is designed to work with the existing processor and power management infrastructure, serving multiple functions including glitch detection, verification, and security monitoring. This multi-functionality improves detection reliability without significantly increasing manufacturing complexity by leveraging existing chip structures.
3Device complexity
If internal glitch signal generation is implemented, then external testing infrastructure is reduced, but use of energy increases due to additional active components
Solution Approach 1:
The glitch signal generation capability is extracted and integrated directly into the chip's self-testing circuit, eliminating the need for external testing infrastructure. This internalization reduces external complexity while the energy consumption is managed through efficient circuit design and controlled activation only during testing phases.
Solution Approach 2:
The self-testing circuit operates periodically or on-demand rather than continuously, generating glitch signals only when verification is needed. This periodic operation reduces energy consumption from the additional active components while maintaining the capability for internal glitch signal generation that eliminates external testing infrastructure.
Data Source
AI summary
Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector. The self-testing glitch signal is further fed back to the glitch controller for verification, and the glitch controller presents an error of the self-testing glitch signal by an error flag.