Chip-Level Graph Compression for Circuit Component Placement
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Solution Overview
Problem
Modern placement engines struggle with computationally intractable chip design due to the uniquification of circuit components, leading to inefficient optimization of wire-length and component placement in integrated circuits.
Innovation Solution
A method is introduced to de-uniquify blocks in a chip-level graph by representing each group of blocks as a single instance using a base block and encoding instance-specific information through linear transformations and sub-graphs, reducing the size of the graph and computational resources required for optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If uniquification of blocks is performed to represent each instance separately in the chip-level graph, then block-specific information and interconnection details are preserved, but the graph size increases exponentially making placement optimization computationally intractable
Solution Approach 1:
The patent merges multiple instances of the same block template into a single representative node in the chip-level graph. Instead of creating separate nodes for each block instance (uniquification), the invention consolidates them by selecting one instance as the representative and encoding relationships to other instances through transformation parameters, thereby reducing graph size while preserving block-specific information.
Solution Approach 2:
The representative block node serves multiple functions: it represents the block template itself, encodes relationships to all other instances through transformation parameters, and maintains interconnection information. This multi-functional approach allows a single node to capture what would otherwise require multiple separate nodes, resolving the contradiction between information preservation and graph complexity.
2Manufacturing precision
If uniquification is performed to encode instance-specific pin location and interconnection information, then placement optimization accuracy is improved, but computational resources required become prohibitive for modern chip scales
Solution Approach 1:
The invention extracts instance-specific information (pin locations, orientations, interconnections) from individual block instances and encodes it in a compact form within the representative node's transformation parameters and sub-graphs. This extraction eliminates the need to process redundant information across multiple uniquified nodes, reducing computational power requirements while maintaining placement optimization accuracy.
Solution Approach 2:
The patent changes the parameter representation from explicit coordinates for each block instance to transformation parameters (translations, rotations, reflections) relative to the representative block. This parameter transformation dramatically reduces the computational state space, enabling placement optimization to achieve the same accuracy with significantly fewer computational resources.
3Reliability
If separate nodes are created for each block instance in the chip-level graph, then detailed interconnection relationships are maintained, but the number of nodes increases at a rate that makes placement optimization computationally intractable
Solution Approach 1:
Instead of creating separate physical nodes for each block instance, the invention creates a single representative node and uses transformation parameters to define relationships to other instances. This copying approach allows the system to reference the same block template multiple times with different transformations, maintaining interconnection relationship accuracy while avoiding the exponential increase in node count that would plague placement optimization performance.
Data Source
AI summary
Aspects of the disclosure provide for eliminating or reducing uniquification of blocks in a chip-level graph of a computer chip, to reduce the size of the graph while still encoding block-specific information. For each group of blocks in the graph generated from a multiply-instantiated block (MIB), a block in the group is selected as a base block. The physical position of the base block is encoded in a reduced graph, and the physical positions of the remaining blocks are encoded as a linear transformation of the physical position of the base block across the face of the chip. Each group of blocks instantiated from the same MIB is represented as a single instance. The reduced graph can be fed into a device configured to perform a circuit component placement process, to identify the placement of circuit components for blocks in the chip in accordance with one or more objectives.