Chip Guard Stress Relief Structure for 3D Memory Reliability
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Solution Overview
Problem
The challenge in improving the operational reliability of three-dimensional nonvolatile memory devices lies in the stress management during the manufacturing process, particularly in the formation of chip guard patterns, which can lead to cracks and abnormal charge accumulation.
Innovation Solution
A semiconductor device design that includes a stress relief pattern on the chip guard region, utilizing doped or undoped silicon layers, and a conductive contact plug penetrating the stress relief pattern to distribute stress and prevent crack formation during the etching process, thereby enhancing the reliability of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip guard patterns are formed during the manufacturing process, then device protection and structural definition are improved, but stress concentration and crack formation occur
Solution Approach 1:
A stress relief pattern is introduced as an intermediary structure between the chip guard pattern and the substrate. This stress relief pattern acts as a mediator that absorbs and distributes the stress generated during etching processes, preventing stress concentration at the chip guard pattern edges and eliminating crack formation while maintaining device protection.
Solution Approach 2:
The stress relief pattern is formed in advance before the chip guard pattern etching process. By pre-positioning this stress-absorbing structure, the system prepares cushioning against the anticipated stress concentration that will occur during subsequent etching operations, thereby preventing crack formation before it can occur.
2Ease of manufacture
If conventional manufacturing processes are used without stress relief structures, then process simplicity is maintained, but stress concentration leads to cracks and abnormal charge accumulation
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming the stress relief pattern first, then forming the chip guard pattern. This segmentation allows each structure to be optimized independently - the stress relief pattern for stress management and the chip guard pattern for device protection - while maintaining overall process simplicity through sequential formation using standard photolithography and etching techniques.
3Productivity
If the chip guard region is directly etched without stress relief structures, then manufacturing steps are reduced, but stress-related defects increase
Solution Approach 1:
The stress relief pattern is formed as a preliminary structure before the chip guard pattern etching process. This preliminary action prepares the substrate by creating a stress-absorbing layer that will be present during subsequent etching operations, thereby preventing stress-related defects without significantly increasing manufacturing complexity.
Data Source
AI summary
There are provided a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a substrate including a chip guard region; a stress relief pattern spaced apart from the substrate and disposed over the chip guard region; a dummy stack structure formed on the stress relief pattern; a conductive contact plug extending downwardly while penetrating the stress relief pattern; and a chip guard pattern in direct contact with the conductive contact plug while penetrating the dummy stack structure.