Chip Heat Dissipation Structure With Stress-Buffering Intermediate Layer
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Solution Overview
Problem
Current semiconductor chip heat dissipation methods face challenges in effectively managing thermal stress and achieving efficient heat dissipation due to large differences in thermal expansion coefficients between metal heat fins and silicon chips, leading to potential device failure, and the use of polymer materials with low thermal conductivity results in high thermal resistance and poor heat dissipation efficiency.
Innovation Solution
A chip heat dissipating structure is developed with a bottom heat fin directly formed on the chip's back surface and side heat fins on its sides, utilizing a metal plate on multiple surfaces for heat dissipation, incorporating an intermediate heat conductive layer and protrusions made of copper, tungsten, or tantalum to buffer thermal stress and enhance heat conduction, while maintaining a low manufacturing cost and efficient process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bottom heat fin is directly connected with the chip to strengthen heat dissipation, then heat dissipation efficiency is improved, but the chip may be damaged due to large thermal expansion coefficient difference between metal heat fin and silicon chip
Solution Approach 1:
An intermediate layer is introduced between the metal heat fin and the silicon chip. This intermediate layer acts as a mediator that accommodates the thermal expansion coefficient difference, preventing direct stress transmission to the chip while maintaining effective heat conduction path from chip to heat fin.
Solution Approach 2:
The heat dissipation structure uses composite material construction with different layers having different properties. The intermediate layer is made of material with thermal expansion coefficient between metal and silicon, creating a gradient structure that smoothly transitions thermal properties and reduces thermal stress.
2Reliability
If a layer of polymer material is formed on the back of the chip to prevent thermal stress impact, then chip protection is improved, but thermal conductivity is low resulting in high thermal resistance and poor heat dissipation efficiency
Solution Approach 1:
The polymer material serves as an intermediate protective layer between the chip and external environment. It provides mechanical protection and stress buffering while maintaining adequate thermal conduction through the package structure, preventing direct impact on the chip.
3Device complexity
If the coefficient of thermal expansion difference between metal copper and silicon chip is large, then thermal stress is generated under temperature impact, but direct connection simplifies the structure
Solution Approach 1:
An intermediate layer is positioned between the copper heat fin and silicon chip to mediate the thermal expansion coefficient mismatch. This layer absorbs differential expansion stresses during temperature cycling, preventing direct mechanical stress on the chip while maintaining structural integrity and simple overall design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively transfers heat from the chip to the heat fin, reduces thermal stress, and achieves a better heat dissipation effect with a lower total thermal resistance, ensuring reliable operation and protecting the chip from thermal damage.
Implementation Method 1
an intermediate structure for buffering temperature-varying stress generated by an internal structure of the package layer and conducting internal heat is set in the package layer
Implementation Method 2
a bottom heat fin is set on a whole surface of a side of the package layer away from the bonding pad of the chip
Data Source
AI summary
Disclosed is a chip heat dissipating structure, a process and a semiconductor device. The structure includes at least a chip and a package layer, the package layer encapsulates the chip, an intermediate structure for buffering temperature-varying stress generated by an internal structure of the package layer and conducting internal heat is arranged in the package layer. In present disclosure, heat generated by chip silicon is transmitted to each heat conductive protrusion through the intermediate heat conductive layer, then heat dissipation is realized through heat fin. The heat fin cooperates with the bonding pad to form double-sided heat dissipation, with good heat dissipation effect, stress deformation of the heat fin does not directly extrude the chip to avoid damage. Structure of both sides of the chip is relatively symmetrical, which balances a stress effect caused by high and low temperatures. Device has strong reliability, and production cost is low.