Semiconductor Chip Height Balancing for Sealing Warp Reduction
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Solution Overview
Problem
Multi-chip package semiconductor devices with chip-layered structures face issues of uneven torsion or strain due to unbalanced sealing members, making it difficult to mount them onto motherboards.
Innovation Solution
A semiconductor device design where the first and second semiconductor chips are mounted on a wiring substrate such that their upper surfaces are at the same height, with a chip-layered structure for the second chip, and a sealing member covering both chips to ensure balanced thickness and reduce torsion or strain during curing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a chip-layered structure with multiple semiconductor chips is used to increase packaging density, then the functionality and integration are improved, but uneven torsion or strain occurs due to unbalanced sealing member thickness
Solution Approach 1:
The patent applies asymmetry by configuring different chip structures (single chip vs. chip-layered structure) in different regions of the wiring substrate. Specifically, a first semiconductor chip is mounted in a first region while a second semiconductor chip with multiple stacked chips is mounted in a second region, creating intentional asymmetric thickness distribution that balances the overall sealing member thickness and prevents warp during curing
Solution Approach 2:
The patent implements local quality by making different regions of the semiconductor device have different structural characteristics. The first region contains a single semiconductor chip while the second region contains a chip-layered structure, allowing each region to be optimized for its specific function while contributing to overall structural balance and preventing device-wide warp
2Ease of manufacture
If a chip-layered structure is used to reduce the number of wiring substrates, then manufacturing cost is reduced, but torsion or strain occurs due to unbalanced sealing member thickness
Solution Approach 1:
The patent applies local quality by creating region-specific chip configurations where a first region has a single chip and a second region has a chip-layered structure. This local differentiation allows the device to use fewer wiring substrates (reducing manufacturing cost) while maintaining sealing balance through carefully designed regional asymmetry
3Reliability
If uneven thickness of sealing member is used to cover chip-layered structure, then all chips can be covered, but uneven torsion or strain is caused during curing
Solution Approach 1:
The patent uses asymmetry to resolve the contradiction between complete chip coverage and torsion resistance. By intentionally creating asymmetric chip configurations (single chip in first region, chip-layered structure in second region), the sealing member achieves both complete coverage of all chips and uniform thickness distribution, preventing torsion and strain during curing
Data Source
AI summary
A semiconductor device has a wiring substrate, a first semiconductor chip, a second semiconductor chip, and a sealing member. The second semiconductor chip has a chip-layered structure with a plurality of semiconductor chip components stacked in the height direction of the semiconductor device. The first semiconductor chip has an upper surface located at the same height from a surface of the wiring substrate as an upper surface of the second semiconductor chip.