Chip ID Generation Circuit for Multi-Chip Package Yield
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Solution Overview
Problem
In semiconductor manufacturing, multi-chip packages with defective memory chips are often discarded as a whole, leading to reduced yields and increased costs, as existing technologies do not allow for flexible reassignment of chip IDs to salvage functional chips.
Innovation Solution
A semiconductor device with a chip ID generation circuit that includes fuse sets and a control circuit to selectively modify chip IDs, allowing for the reassignment of IDs when a chip is determined defective or to be stopped, enabling the chip to operate as a master or slave chip, thereby increasing manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory chips with unique fixed IDs are used in multi-chip packages, then chip identification is simple and reliable, but the entire package must be discarded when any chip is defective, reducing manufacturing yield
Solution Approach 1:
The chip ID is changed from a fixed value to a dynamically reassignable value. The patent implements fuse sets that can be selectively programmed to assign different IDs to chips based on their operational status, allowing the system to adapt to defects by reassigning IDs to functional chips rather than discarding the entire package.
Solution Approach 2:
The chip ID parameter is made changeable through the fuse set mechanism. By programming different fuse sets, the chip ID can be modified to reflect the actual operational status of chips in the package, enabling flexible reassignment when defects are detected and allowing functional chips to be utilized.
2Ease of manufacture
If chip IDs are fixed during manufacturing, then the manufacturing process is simple and fast, but defective chips cannot be distinguished from functional chips, leading to waste of functional chips
Solution Approach 1:
The patent prepares multiple fuse sets in advance during chip manufacturing, but the actual ID assignment is deferred until after packaging and testing. This preliminary preparation allows for rapid initial manufacturing while enabling subsequent ID reassignment to identify and utilize functional chips that would otherwise be discarded with defective ones.
Solution Approach 2:
The ID assignment function is extracted from the chip fabrication process and separated into a post-packaging programming step. This allows the main manufacturing process to remain simple and fast, while the ID assignment is performed separately based on actual chip performance, preventing waste of functional chips.
3Device complexity
If all chips in a multi-chip package are treated as a single unit, then package management is simple, but functional chips cannot be individually utilized when some chips are defective
Solution Approach 1:
The patent segments the chip identification system by implementing individual fuse sets for each chip, allowing independent ID assignment and control. This enables the system to treat chips as individual units rather than a single package unit, facilitating selective utilization of functional chips while isolating defective ones.
Solution Approach 2:
The fuse set mechanism provides universal functionality across all chips in the package, enabling each chip to have its ID independently configured. This multi-functionality allows the same hardware structure to serve both simple package management and individual chip identification/utilization based on operational status.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution increases manufacturing yields and reduces costs by allowing functional chips in a multi-chip package to be reassigned IDs, preventing the entire package from being discarded due to a single defective chip, thus optimizing chip utilization.
Implementation Method 1
The chip ID generation circuit may include: a chip ID fuse unit including at least two fuse sets that selectively program a chip ID of the chip
Data Source
AI summary
Provided is a semiconductor device including chip identification (ID) generation circuits. The semiconductor device may be a multi-chip package including a plurality of memory chips, and each of the memory chips includes a chip ID generation circuit configured to selectively modify a chip ID of a corresponding memory chip. The chip ID generation circuit determines the chip ID of the memory chip by testing the chip ID of the memory chip by using a mode register, and selectively programs the chip ID of the memory chip by using at least two fuse sets. The chip ID generation circuit may block an output of the chip ID of the memory chip when the memory chip is determined as a defective chip or is selected to stop its use.