Semiconductor Chip Identification Marks for Yield Learning
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Solution Overview
Problem
It is challenging to trace the origins of failed semiconductor chips, hindering the correlation of failures with inline manufacturing data and making root cause analysis difficult, especially during product development and yield learning.
Innovation Solution
A semiconductor chip is designed with a first mark to identify its position within an exposure field, featuring a matrix in a first layer and a second mark within the matrix to indicate the exposure field on a wafer, allowing for optical reading and tracing of the chip's position, wafer number, and lot number.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor chip samples are tracked during product development and qualification, then yield learning and process split tracking improve, but the complexity of tracking and correlating failures with manufacturing data increases
Solution Approach 1:
The identification system is segmented into multiple hierarchical levels: exposure field marks identify the exposure field, matrix structures identify the wafer, and individual chip marks identify specific chip positions. This segmentation allows tracking of multiple samples without creating a single complex tracking system, as each level can be independently managed and correlated.
Solution Approach 2:
Identification marks are formed on the chips during the manufacturing process itself, before the chips are packaged and shipped. This preliminary action ensures that the identification information is already embedded in the chips, eliminating the need for complex post-manufacturing tracking systems and enabling direct correlation of failures with manufacturing data.
2Loss of information
If identification marks are formed on semiconductor chips, then the ability to trace chip origins and perform root cause analysis improves, but the manufacturing process complexity increases
Solution Approach 1:
The identification marks are merged with the existing manufacturing process by forming them during the exposure step using specialized reticles. This combining of functions means that the same equipment and process steps used for manufacturing the chips are also used to form the identification marks, eliminating the need for separate marking equipment and processes.
Solution Approach 2:
The exposure tool is given multi-functionality by using it both for manufacturing the chips and for forming the identification marks. This universal use of equipment means that no additional specialized equipment is needed, and the same reticle can serve both as a manufacturing template and as a marking template, simplifying the overall manufacturing process.
3Ease of manufacture
If only limited lot-level tracking is performed, then manufacturing simplicity is maintained, but the ability to correlate failures with specific wafers and positions is lost
Solution Approach 1:
The tracking system transitions from a single dimension (lot-level) to multiple dimensions by adding exposure field identification, wafer identification through matrix structures, and chip position identification. This multi-dimensional approach provides precise failure correlation while maintaining manufacturing simplicity because each dimension is added as a separate, independent marking layer that can be formed using the same exposure process.
Data Source
AI summary
A semiconductor chip includes a first mark for identifying a position of the chip within an exposure field. The semiconductor chip includes a first matrix in a first layer of the chip and a second mark within the first matrix identifying a position of the exposure field on a wafer.