Communication Chip Online Function Safety Testing via Idle Time Slot Injection
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Solution Overview
Problem
Current communication chip testing methods have low test coverage rates and excessive resource consumption, as they primarily focus on offline quality testing and lack effective function safety assessment, which is essential for ensuring the reliability of communication chips in industries like mobile communications and wireless networks.
Innovation Solution
A method and apparatus for performing online function safety tests on communication chips by detecting idle time slots and using test vectors to process data frames, allowing for real-time comparison of chip processing results with standard results, thereby improving test coverage and reducing resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Parity or ECC method is used for function safety test, then test coverage rate is improved, but test nodes cannot be accurately distinguished causing low measurement precision
Solution Approach 1:
The patent segments the test vector into multiple code blocks, where each code block corresponds to a specific test node. This segmentation enables accurate identification and distinction of individual test nodes while maintaining comprehensive function safety test coverage through the distributed parity bits across multiple code blocks.
2Reliability
If Redundancy Design or Dual Lock step method is used, then function safety is improved, but chip resources and performance are sacrificed
Solution Approach 1:
The patent extracts the safety test function from the normal data transmission process by utilizing idle time slots. The test vectors are injected during these idle periods without requiring redundant chip resources or performance sacrifice, as the test operations are performed using existing chip resources during otherwise unused time periods.
Solution Approach 2:
The patent implements periodic testing by utilizing idle time slots that occur regularly during communication operations. Test vectors are periodically injected into these idle slots, enabling continuous function safety verification without requiring dedicated redundant resources, as the same chip resources are reused during idle periods.
3Reliability
If offline test method is used, then function safety test can be performed, but the communication chip cannot be tested in real-time operation
Solution Approach 1:
The patent performs preliminary testing actions during idle time slots before the chip enters its next operational state. Test vectors are prepared and injected in advance during these idle periods, allowing the chip to be tested while maintaining its running state, thus achieving real-time testing capability without requiring offline operation.
Solution Approach 2:
The patent transforms the static offline testing approach into a dynamic online testing method by adapting the test injection timing to the chip's operational state. The system dynamically identifies and utilizes idle time slots during normal operation to inject test vectors, enabling the chip to be tested in real-time while maintaining its running state rather than requiring shutdown for testing.
Data Source
AI summary
Provided test method and apparatus of communication chip, device and medium. The test method of communication chip includes receiving end test method and transmitting end test method. The receiving end test method of the communication chip includes: an idle time slot of the receiving end of the communication chip is detected in a running process of the communication chip; a test vector is generated, and a standard result corresponding to the test vector is generated; a data frame containing the test vector is constructed, and the data frame is sent to the receiving end of the communication chip in the idle time slot to enable the receiving end of the communication chip to process the data frame; and a chip processing result uploaded by the receiving end of the communication chip is received, and the standard result is compared with the chip processing result.