Chip Inductor with Expanded Coil Routing for High Q-Value

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Solution Overview

Problem

Conventional inductors have a restricted forming region for the coil conductor, making it difficult to increase inductance and reduce resistance, thereby limiting the improvement of the Quality Factor (Q-value).

Innovation Solution

A chip inductor design with a spiral coil conductor routed to regions outside and between external terminals, increasing the planar area and number of windings, and incorporating an insulating layer to suppress parasitic capacitance, which enhances the Q-value.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the coil conductor is restricted to form only between external terminals, then the device structure is simple, but the inductance cannot be increased and resistance cannot be reduced

Engineering Contradiction:
ImproveQ-valueVSAvoidcoil conductor routing
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The coil conductor routing is extended from the traditional restricted area between external terminals to include regions outside the external terminals and regions facing the external terminals at the main surface. This dimensional expansion of the routing area allows for increased planar area and number of windings, thereby increasing inductance and reducing resistance without fundamentally changing the device structure

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the coil conductor planar area is increased, then inductance increases and resistance decreases, but parasitic capacitance fluctuations occur

Engineering Contradiction:
Improveinductance and resistanceVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An insulating layer is introduced as an intermediary between the coil conductor and the substrate. This insulating layer suppresses parasitic capacitance fluctuations that occur when the coil conductor planar area is increased, allowing the design to achieve higher inductance and lower resistance without suffering from parasitic capacitance issues

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10566126B2Chip inductor and manufacturing method thereof
Publication Date: 2020.02.18 ROHM CO LTD
  • US10566126B2 patent drawing
  • US10566126B2 patent drawing
  • US10566126B2 patent drawing

AI summary

A chip inductor includes a substrate having a main surface, an insulating layer covering the main surface of the substrate, an external terminal formed on the insulating layer, and a coil conductor of a spiral-shape routed to a region outside the external terminal and a region facing the external terminal at the main surface of the substrate.