Chip Inductor Plating Thickness Control
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Solution Overview
Problem
The existing manufacturing process for thin-film inductors faces challenges in achieving uniform plating thickness and direct current resistance (Rdc) characteristics due to excessive plating on outermost and innermost coil conductor patterns, leading to inadequate copper ion supply and uneven plating distribution.
Innovation Solution
The solution involves forming coil conductor patterns with a pattern plating layer and a first plating layer, where the thickness of the first plating layer of the outermost and innermost coil conductor patterns is greater than that of the inner coil conductor patterns, and a second plating layer is added on top, ensuring uniform thickness and minimizing direct current resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anisotropic plating is applied to grow plating layers only above the coil, then direct current resistance is improved, but plating thickness distribution becomes non-uniform across different coil positions
Solution Approach 1:
The patent implements local quality by specifying that the first plating layer has a greater thickness at the outermost and innermost coil conductor patterns compared to inner coil conductor patterns. This localized thickness variation compensates for the non-uniform copper ion distribution during anisotropic plating, ensuring that all coil conductor patterns achieve consistent effective plating thickness and desired direct current resistance characteristics.
Solution Approach 2:
The patent changes the plating thickness parameter selectively across different coil positions. By designing the first plating layer with position-dependent thickness (greater at outermost and innermost layers, smaller at inner layers), the patent optimizes the effective plating area and direct current resistance characteristics while compensating for the non-uniform plating deposition inherent in anisotropic plating processes.
2Area of stationary object
If outermost and innermost plating layers are allowed to plate excessively without adjacent layers, then plating coverage is improved, but copper ion supply becomes insufficient leading to slow plating growth
Solution Approach 1:
The patent applies preliminary action by pre-designing the first plating layer with greater thickness at the outermost and innermost coil conductor patterns before the secondary plating process. This preliminary thickness compensation ensures that even though these edge positions experience slower plating growth due to insufficient copper ion supply, they still achieve the required effective plating thickness and coverage for optimal direct current resistance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maximizes the area of the coil conductor pattern, minimizes direct current resistance, and achieves consistent plating thickness, thereby enhancing the inductor's performance and manufacturing efficiency.
Implementation Method 1
a plated area is important to enhance direct current resistance Rdc, an important characteristic of the inductor. To this end, an anisotropic plating scheme of applying high current density to only grow plating layers in a direction above a coil has been applied.
Implementation Method 2
it may be used to configure a resonance circuit for amplifying a signal within a specific frequency band via a combination with a capacitor using electromagnetic characteristics
Data Source
AI summary
A chip electronic component includes a magnetic main body including an insulating substrate and a coil conductor pattern disposed on at least one surface of the insulating substrate, and external electrodes formed on opposite ends of the magnetic main body so as to be connected to an end of the coil conductor pattern. The coil conductor pattern includes a pattern plating layer and a first plating layer disposed on the pattern plating layer, and a thickness of the first plating layer of innermost and outermost coil conductor patterns of the coil conductor pattern is greater than a thickness of the first plating layer of an inner coil conductor pattern disposed between the innermost and outermost coil conductor patterns.