Chip Interconnect Oxide Reduction Without ULK Layer Damage
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Solution Overview
Problem
Conventional chip manufacturing processes face issues with feature size deviations and reduced reliability due to adverse chain reactions between process steps, particularly in the back end of line, leading to increased resistivity and potential damage to the ultra-low dielectric constant (ULK) layer.
Innovation Solution
A chip preparation method involving the formation of a first conductive pattern with a second metal film having higher reactivity than the first metal, allowing for an oxidation-reduction reaction to reduce oxide on the first conductive pattern's surface, thereby reducing resistance and avoiding damage to the ULK layer through plasma pre-cleaning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional plasma pre-cleaning is used to remove oxide from the first conductive pattern surface, then oxide removal is achieved, but damage to the ULK layer occurs and chip reliability decreases
Solution Approach 1:
The patent converts the harmful oxide layer into a beneficial component by using a second metal with higher reactivity to reduce the oxide of the first metal back to metallic form. The oxidation step that creates the harmful oxide is followed by a reduction step using the second metal, which has greater reactivity, thereby converting the harmful oxide into beneficial metallic conductive material and improving chip reliability without damaging the ULK layer
Solution Approach 2:
The patent changes the chemical state of the first metal by controlling oxidation and reduction parameters. The first metal is oxidized to form oxide, then reduced by the second metal back to metallic form. This parameter change approach allows removal of oxide without plasma pre-cleaning, avoiding ULK layer damage while maintaining conductive properties
2Manufacturing precision
If multiple process steps are used in back end of line manufacturing, then wiring layer formation is achieved, but adverse chain reactions occur causing feature size deviation and reduced reliability
Solution Approach 1:
The patent merges the oxide removal function and the conductive pattern formation function into a single integrated process. By using the second metal's reactivity to reduce the oxide in-situ, the process eliminates the need for separate plasma pre-cleaning steps, reducing the total number of process steps and preventing adverse chain reactions between steps while maintaining manufacturing precision
3Reliability
If oxide layer remains on the first conductive pattern surface, then plasma pre-cleaning can be avoided, but connection resistance increases and chip performance decreases
Solution Approach 1:
The patent converts the oxide layer from a harmful high-resistance material into a beneficial source of metallic conductive material. The second metal with higher reactivity reduces the oxide back to metallic form, creating a low-resistance conductive interface. This eliminates connection resistance issues while avoiding plasma pre-cleaning damage to the ULK layer
Solution Approach 2:
The second metal acts as an intermediary substance that facilitates the conversion of oxide to metallic conductive material. By introducing this intermediate reduction step, the patent achieves low connection resistance without requiring aggressive plasma pre-cleaning, thereby protecting the ULK layer and improving overall chip reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves chip reliability by lowering connection resistance and preventing damage to the ULK layer, resulting in a chip with lower resistivity and enhanced performance.
Implementation Method 1
enabling the second metal to react with the oxide of the first metal, to reduce at least a part of the oxide of the first metal on the top surface of the first conductive pattern to the first metal
Implementation Method 2
the first metal on a top surface of the first conductive pattern is oxidized into oxide of the first metal
Data Source
Figure 1A~1B
Figure 1C
Figure 1D
AI summary
Embodiments of this application provide a chip, a chip preparation method, and an electronic device, and relate to the field of semiconductor technologies, to improve chip reliability. The chip includes a substrate, an electronic element, a first wiring layer, and a second wiring layer. The electronic element includes a conductive portion and is disposed on the substrate. The first wiring layer is disposed on a side that is of the electronic element and that is away from the substrate. The first wiring layer includes a first conductive pattern, and the first conductive pattern is coupled to the conductive portion. The second wiring layer is disposed on a surface of the first wiring layer. The second wiring layer includes a second conductive pattern and a third conductive pattern, the third conductive pattern includes a first portion disposed between the second conductive pattern and the first conductive pattern, and the first portion is in contact with the first conductive pattern and is coupled to the second conductive pattern. A material of a top surface of the first conductive pattern includes a first metal element, and a material of the first portion includes oxide of second metal. Reactivity of the second metal is greater than reactivity of the first metal, and the oxide of the second metal is a conductive material.