On-Chip Interconnect Topologies for Low-Latency SoC Traffic
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Solution Overview
Problem
As the number of processors and components on a System on a Chip (SOC) increases, the bandwidth requirements between memory controllers and components overwhelm the interconnect, leading to increased latency and reduced performance benefits.
Innovation Solution
Implementing multiple physically and logically independent networks within the SOC, each optimized for specific types of traffic, such as CPU, I/O, and relaxed order networks, with dedicated network switches and virtual channels to manage communication efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processors and components on the SOC is increased, then the performance and functionality of the device are improved, but the bandwidth requirements between memory controllers and components increase, overwhelming the interconnect and leading to increased latency
Solution Approach 1:
The patent divides the interconnect into multiple independent networks (first network, second network, third network) that are physically and logically separate. Each network handles specific types of traffic: the first network handles CPU traffic with strict ordering, the second network handles I/O traffic with relaxed ordering, and the third network handles memory controller traffic. This segmentation allows concurrent communication on multiple networks without interference, thereby maintaining low latency while supporting increased numbers of processors and components.
2Productivity
If multiple independent networks are implemented, then bandwidth and latency performance are improved, but the device complexity and number of interconnect resources increase
Solution Approach 1:
The patent applies different quality attributes to different networks based on their specific requirements. The first network is designed with strict ordering constraints for CPU traffic, the second network has relaxed ordering for I/O traffic, and the third network is optimized for memory controller communications. Each network has tailored error handling, flow control, and routing characteristics appropriate to its traffic type, rather than applying a uniform design to all traffic. This local optimization achieves high performance while managing complexity through targeted design decisions.
Solution Approach 2:
The patent implements dynamic resource allocation and routing across the multiple networks. Network switches dynamically route packets based on traffic type, source, and destination. The system can adaptively select which network to use for different communications, and can dynamically allocate bandwidth and resources based on current system conditions and traffic demands. This dynamic behavior allows the interconnect to efficiently handle varying workloads while maintaining performance.
Data Source
AI summary
In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.