Chip-to-Chip Interconnect Testing with Phase-Shifted Signals
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Solution Overview
Problem
Testing and ensuring proper operation of integrated semiconductor dice in multi-die packages is challenging due to defects in micro bump interconnects, such as bridging, foreign material presence, and misalignment, which affect signal transmission between chips.
Innovation Solution
A built-in self-test solution with redundant lanes and single line stress tests is implemented to identify and repair defects in die-to-die interconnects, allowing for on-die repair calculation and cross-die clock tuning, thereby improving yield and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If multiple semiconductor dice are integrated into a single package to reduce power consumption and form factor size, then power consumption and device size are reduced, but testing and ensuring proper operation of interconnects between chips becomes challenging
Solution Approach 1:
The patent implements preliminary testing actions by integrating test circuits and test logic directly into the chiplets before final packaging. This allows interconnect defects to be detected early in the manufacturing process, enabling sort-level testing (individual chiplet testing) and class-level testing (packaged device testing) to ensure proper operation before the chips are permanently assembled together.
Solution Approach 2:
The patent introduces intermediary test circuits and test structures as mediators between the chiplets and testing equipment. These include test access ports, built-in self-test (BIST) circuits, and dedicated test interconnects that facilitate the detection and characterization of interconnect defects without requiring direct access to all internal signal paths.
2Quantity of substance
If micro bump interconnects are used to connect chiplets, then integration density is increased, but defects such as bridging, foreign material presence, and misalignment occur affecting signal transmission
Solution Approach 1:
The patent performs preliminary alignment verification and interconnect quality assessment during the chiplet fabrication and packaging processes. Test structures are activated before final product completion to detect misalignment, bridging, or foreign material contamination in micro bump interconnects, allowing for rework or rejection of defective assemblies.
Solution Approach 2:
The patent replaces purely mechanical alignment methods with electro-magnetic based detection methods. Electrical test signals are transmitted through the micro bump interconnects to detect defects such as bridging (unintended electrical connections), opens (broken connections), or foreign material presence, providing more sensitive and accurate defect detection compared to mechanical inspection alone.
3Productivity
If built-in self-test solution with redundant lanes is implemented to identify and repair defects, then yield is improved and manufacturing costs are reduced, but device complexity increases
Solution Approach 1:
The patent implements multi-functional test circuits that can perform multiple testing functions using the same hardware resources. The built-in self-test (BIST) logic can test both individual chiplets (sort-level) and packaged assemblies (class-level), and can detect various defect types (bridging, opens, misalignment) using unified test methodologies, reducing the need for separate dedicated test circuits for each function.
Solution Approach 2:
The patent utilizes parameter changes in electrical characteristics (such as signal transmission time, signal amplitude, impedance) to detect interconnect defects. By monitoring changes in these electrical parameters during test signal transmission, the system can identify defects without requiring complex structural modifications, thereby managing device complexity while improving yield.
Data Source
AI summary
Embodiments herein relate to a test, repair, and diagnostic solution for chip-to-chip interconnects. In one aspect, on a first chip, a first finite state machine (FSM) is coupled to a set of transmit lanes. To test each transmit lane, one at a time, the first FSM is to apply a first periodic signal to a transmit lane under test and concurrently apply a second periodic signal to other transmit lanes of the set of transmit lanes, where a phase of the first periodic signal is opposite to a phase of the second periodic signal. A comparator compares a detected signal on the lane under test to an expected response. The comparator can be on the first chip, when the first chip is tested alone, or on a second chip, where the two chips are tested together.