Chip Interconnect Using Virtual Channels and Credit Flow Control

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In current on-chip communication protocols, pipeline stage registers divide long timing paths for forward-going data flows but not for backward-going flow control signals, resulting in unavoidable combinatorial logic between registers at chip IOs, which complicates inter-chip communication.

Innovation Solution

A credit-based flow control protocol is implemented between chips using a single packet-based on-chip and inter-chip network, allowing registered inputs and outputs by separating data and flow control signals, eliminating the need for combinatorial logic between registers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If pipeline stage registers are added to divide long timing paths for forward-going data flows, then data transfer timing is improved, but backward-going flow control signals still have combinatorial logic between registers

Engineering Contradiction:

Improvedata transfer timingVSAvoidcombinatorial logic between registers

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent segments the flow control mechanism by introducing separate pipeline registers for forward-going data flows and backward-going flow control signals. This segmentation allows each signal type to have its own registered path, eliminating combinatorial logic between registers for both directions while maintaining timing performance.

Inventive Principle:

Principle #1Segmentation

2Speed

If registers are added at chip outputs and inputs to eliminate combinatorial logic, then signal propagation is improved, but flow control signaling becomes more complex

Engineering Contradiction:

Improvesignal propagation speedVSAvoidflow control signaling

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent segments the signaling protocol into distinct forward-going data flow signals and backward-going flow control signals, each with dedicated pipeline registers. This segmentation simplifies flow control signaling by preventing combinatorial logic interactions while enabling direct registered connections at chip I/Os for high-speed propagation.

Inventive Principle:

Principle #1Segmentation

3Loss of time

If a single address space protocol is used for transparent communication, then encoding and decoding latency is reduced, but physical implementation benefits of packet-based protocols are lost

Engineering Contradiction:

Improveencoding and decoding latencyVSAvoidphysical implementation benefits

Core Design Contradiction:

Loss of timeVSEase of manufacture

Solution Approach 1:

The patent merges packet-based communication with transparent address space access by implementing packet-based protocols at the physical layer while maintaining transparent addressing at the protocol layer. This combination achieves both low encoding/decoding latency through transparent address spaces and physical implementation benefits through packet-based routing and flow control.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS8824295B2Link between chips using virtual channels and credit based flow control

Publication Date: 2014.09.02 QUALCOMM TECHNOLOGIES INC

AI summary

A system and method is disclosed for multiple chips in which the connection between chips is made with registered inputs and registered outputs. This is achieved using a credit-based flow control protocol between the chips. The connection is made as part of a single packet-based on-chip and between-chip network with a common address space between the two chips.