Chip Interconnection Bridge for High-Density Power Distribution
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Solution Overview
Problem
Conventional semiconductor packaging technologies, such as ceramic-based and organic laminate substrates, are limited in achieving high-density I/O flip-chip connections and die-to-die interconnections due to constraints on contact pad pitch, line width, and line spacing, and they also hinder vertical power distribution, leading to increased voltage drop and IR heating.
Innovation Solution
The development of multi-chip package structures incorporating chip interconnection bridge devices that provide high I/O interconnect density and vertical power distribution through fine-pitch wiring and vias, allowing direct power and ground connections from the package substrate to IC dies, thereby overcoming the limitations of conventional substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ceramic-based or organic laminate substrates are used for MCM packaging, then the package structure can be constructed with standard fabrication processes, but the contact pad pitch, line width, and line spacing cannot be reduced below certain limits, preventing high-density I/O flip-chip connections and die-to-die interconnections
Solution Approach 1:
The patent introduces a silicon interposer layer between the package substrate and IC dies, adding a vertical dimension to the interconnection architecture. This interposer enables fine-pitch wiring and TSVs to achieve contact pad pitches and line widths that are impossible with conventional substrate technologies alone, while keeping the package substrate fabrication processes standard.
Solution Approach 2:
The silicon interposer acts as an intermediary component that mediates between the coarse-pitch package substrate and the fine-pitch IC dies. It provides the fine-pitch wiring and TSVs needed for high-density interconnections, while the package substrate maintains its standard fabrication processes, thus resolving the contradiction between manufacturing precision and ease of manufacture.
2Productivity
If IC chips with increasing integrated functionality and smaller footprint sizes are developed, then the I/O count and I/O density increase, but the conventional substrate technologies cannot support the tight pitches needed for high-density I/O flip-chip connections and high-density die-to-die interconnections
Solution Approach 1:
By adding the silicon interposer dimension, the system achieves fine-pitch wiring capabilities (10 microns or less) that enable high I/O density connections. The interposer's TSVs and multi-layer wiring provide the necessary pitch reduction without requiring the package substrate itself to be manufactured with ultra-fine features.
Solution Approach 2:
The patent changes the pitch parameter from the package substrate level to the interposer level. The interposer is fabricated with fine-pitch features (10 microns or less) that enable high-density interconnections, while the package substrate maintains larger, more manufacturable pitch dimensions.
3Productivity
If silicon interposers with TSVs are used to achieve high wiring density for I/O redistribution and die-to-die communication, then the I/O density increases, but the fabrication costs and complexity increase significantly
Solution Approach 1:
The patent segments the packaging system into distinct functional layers: the package substrate for mechanical support and power distribution, the silicon interposer for fine-pitch signaling and interconnection, and the IC dies for functionality. This segmentation allows each layer to be optimized independently, reducing overall fabrication complexity.
Solution Approach 2:
The silicon interposer serves multiple functions: it provides fine-pitch wiring for I/O redistribution, contains TSVs for vertical interconnections, and enables both die-to-die communication and power distribution. This multi-functionality reduces the need for additional specialized components, thereby reducing overall device complexity.
4Reliability
If conventional substrate technologies are used, then the package structure can be constructed with standard processes, but vertical power distribution is hindered, leading to increased voltage drop and IR heating
Solution Approach 1:
The silicon interposer adds a vertical dimension to power distribution through TSVs, enabling direct vertical power paths from the package substrate through the interposer to the IC dies. This vertical power distribution path significantly reduces the horizontal current path length, thereby reducing voltage drop and IR heating.
Solution Approach 2:
The silicon interposer acts as an intermediary that provides low-impedance vertical power distribution paths. Its highly conductive TSVs and power planes mediate between the package substrate power pins and the IC die power pads, minimizing voltage drop and thermal issues that would occur with conventional lateral power distribution through the substrate.
Data Source
AI summary
Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.