Chip Interconnection Networks with Separate Request and Response Paths
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Solution Overview
Problem
Existing interconnection network architectures for semiconductor chips lack flexibility to adapt to changing application-oriented requirements and increasing numbers of communicating elements, leading to inefficiencies in wire usage and integration speed.
Innovation Solution
A system with two separate communication networks for request and response messages, organized into independent layers, allowing autonomous management and optimization of each layer, reducing wire requirements by sharing data and control information on the same wires, and enabling configuration via software.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single communication protocol is used for interconnecting functional blocks, then adaptability to changing application requirements is improved, but the complexity of managing different operating characteristics (data size, frequency) increases
Solution Approach 1:
The communication protocol is segmented into multiple independent layers (transport layer, physical layer). Each layer can be independently configured and optimized for different operating characteristics, allowing the system to adapt to various application requirements without increasing overall protocol complexity. The transport layer handles data size variations while the physical layer manages frequency differences.
2Ease of operation
If physically separate request and response networks are used, then autonomous management of requests and responses is improved, but the number of wires required increases
Solution Approach 1:
The same physical wires are used to convey both data packets and control information (addresses, flow control signals, packet delimiting). This multi-functional use of wires reduces the total wire count while maintaining the autonomy of request and response networks through protocol-level separation.
3Ease of manufacture
If data buses are used for interconnecting functional blocks, then ease of implementation is improved, but flexibility for rapid adaptation to technological changes deteriorates
Solution Approach 1:
The system uses configurable protocol layers that can be dynamically adjusted to match different application requirements and technological changes. The transport layer and physical layer can be independently reconfigured, allowing rapid adaptation while maintaining the straightforward implementation of bus-based interconnection.
4Quantity of substance
If wire cost becomes dominant over logic gate cost, then the importance of wire optimization increases, but the complexity of assessing wire cost effectiveness increases
Solution Approach 1:
The patent combines data transmission and control information transmission over the same wires. By merging these functions into a single packet-based protocol, the system reduces the total wire count and simplifies the assessment of wire cost effectiveness, as there is only one interconnection network to evaluate rather than separate data and control paths.
Data Source
AI summary
The system of interconnections (20) for external functional blocks on a chip provided with a single configurable communication protocol, comprises two physically separate communication networks (21, 22): a request network (21) for transmitting request messages from an initiating block (23, 24, 25, 26) to a recipient block (27, 28, 29, 30, 31) and a response network (22) for transmitting response messages from a recipient block (27, 28, 29, 30, 31) to an initiating block (23, 25, 26). The response messages include additional information making said request (21) and response (22) networks able to respectively manage the request messages and the response messages independently.