Interfacing Bars for Scalable Logic-Memory Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Scalable systems face challenges in independently scaling logic and memory while maintaining cost-effectiveness, as increasing one parameter often results in tradeoffs with other parameters such as bandwidth, power, and latency, particularly in DRAM-based systems.
Innovation Solution
The use of interfacing bars to couple adjacent chips, enabling increased chip-to-chip connection periphery and bandwidth with mitigated latency, and allowing for modular scaling of logic and memory through various packaging configurations such as chip-on-wafer and 2.5D packaging, which supports metal stacks, hybrid bonding, and optical interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM bandwidth is increased, then memory performance is improved, but other parameters such as power consumption and latency deteriorate
Solution Approach 1:
The system is divided into multiple independent memory channels, each handling a portion of the total bandwidth requirement. This segmentation allows the system to achieve high aggregate bandwidth while each individual channel operates at moderate speeds with lower power consumption, thus resolving the contradiction between total bandwidth and per-channel power usage.
Solution Approach 2:
The patent transitions from a single-plane memory architecture to a multi-plane three-dimensional memory structure. By stacking multiple memory planes vertically and enabling independent access to each plane, the system achieves increased bandwidth through the third dimension (vertical stacking) without increasing the power consumption of individual memory cells, as each plane operates independently at standard power levels.
2Quantity of substance
If memory capacity is increased, then storage capability is improved, but system cost and complexity increase
Solution Approach 1:
The multi-plane memory structure serves multiple functions simultaneously: it provides increased memory capacity through vertical stacking, enables independent parallel access to different planes for enhanced bandwidth, and maintains a unified memory interface that simplifies controller design. This multi-functionality allows the system to achieve higher capacity without proportionally increasing complexity, as the same structural elements serve both capacity and performance goals.
Solution Approach 2:
The patent implements a nested hierarchical structure where multiple memory planes are stacked vertically within a single memory package, with each plane containing further nested memory cell arrays. This nested arrangement allows capacity to scale by adding more nested levels rather than expanding laterally, which would increase complexity. The nested structure enables capacity expansion while maintaining a compact, manageable form factor with shared control logic.
3Adaptability or versatility
If logic and memory are scaled independently, then system customization is improved, but integration difficulty and cost increase
Solution Approach 1:
The standardized multi-plane memory package design serves as a universal building block that can be integrated with various logic architectures and configurations. The uniform interface and modular structure allow the same memory package to be adapted to different system requirements (varying bandwidth, capacity, and power needs) without requiring custom memory designs, thus enabling system customization while maintaining ease of manufacture through standardized components.
Solution Approach 2:
The system architecture segments memory and logic into independent modular units that can be selectively combined. The multi-plane memory is divided into independently addressable planes, and logic functions are separated into discrete components, allowing each to be scaled and configured independently according to system requirements. This segmentation enables customization of the final system by selecting appropriate combinations of standardized modules rather than requiring custom integrated designs.
Data Source
AI summary
Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.