Chip I/O Scan Data Serialization for Reduced IC Test Time
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Solution Overview
Problem
Existing integrated circuit (IC) test methods face challenges in reducing test time and cost as IC complexity grows, with current solutions like scan compression, USB/PCIe I/O interfaces, and IEEE 1149.10 standard being insufficient for modern large ICs due to protocol-specific packetization requirements and hardware limitations.
Innovation Solution
An integrated circuit verification system using a device under test (DUT) with internal test data de-serializer and response data serializer, enabling serialization and de-serialization of scan test data through general-purpose I/O ports without packetization, allowing seamless data transfer between ATE and DUT without specialized I/O interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If specialized high-speed I/O interfaces (USB, PCIe) are used for scan test data delivery, then test time is reduced, but protocol-specific packetization requirements and additional hardware complexity are introduced
Solution Approach 1:
The patent introduces a serializer/de-serializer interface as an intermediary component that bridges the ATE and the IC scan logic. This intermediary converts parallel scan data to serial format for transmission through standard I/O pins, eliminating the need for specialized high-speed interfaces while maintaining efficient data transfer. The serializer/de-serializer handles the protocol conversion and data formatting, allowing standard I/O pins to function as high-speed communication channels without requiring specialized hardware.
Solution Approach 2:
The patent changes the data transmission parameter from parallel to serial format. By serializing the scan test data before transmission through standard I/O pins, the system achieves high-speed communication without requiring specialized interfaces. The serializer converts multiple parallel data bits into a sequential stream that can be transmitted through standard I/O pins at high speeds, and the de-serializer reverses this process at the receiving end, enabling efficient data transfer using existing hardware infrastructure.
2Speed
If IEEE 1149.10 standard is used for scan test data delivery, then high-speed operation is enabled, but ATE equipment modification is required due to packet format requirements
Solution Approach 1:
The serializer/de-serializer acts as an intermediary that translates between the ATE's standard data format and the high-speed serial transmission format. This intermediary component enables the ATE to communicate with the IC at high speeds without requiring modifications to the ATE itself. The serializer handles the conversion of parallel data to serial format and manages the timing and protocol details, allowing existing ATE equipment to interface with high-speed I/O pins through this translation layer.
Solution Approach 2:
The patent implements self-service by embedding the serializer/de-serializer functionality within the IC itself rather than requiring external hardware or ATE modifications. The IC's built-in serializer/de-serializer handles all the protocol conversion and data formatting tasks, allowing the ATE to simply transmit standard parallel data which is then automatically converted to serial format for high-speed transmission through the I/O pins. This eliminates the need for ATE modification while enabling high-speed operation.
3Loss of time
If scan compression is used to reduce test payload, then test time is reduced, but it becomes insufficient for very large modern ICs
Solution Approach 1:
The patent adds a new dimension to the testing approach by introducing serial transmission through standard I/O pins, which fundamentally changes how data is moved between the ATE and the IC. Instead of relying solely on data compression to reduce payload size, the system uses serial transmission to increase the effective data transfer rate. This dimensional change from parallel to serial transmission enables the system to handle very large ICs that cannot be tested effectively with compression alone, as the serial interface provides a new pathway for high-speed data exchange that complements compression techniques.
Data Source
AI summary
An integrated circuit verification system including automatic test equipment (ATE) and a device under test (DUT) having an internal test data de-serializer and test response data serializer. Specifically, the de-serializer of the DUT is able to de-serialize a test pattern or scan test data generated and received from an ATE at a general-purpose I/O pin (or functional pin) of the DUT for testing a circuit under test (CUT) of the DUT and then serialize the response to the test data with the serializer for output back to the ATE via the same or a different general-purpose I/O pin (or functional pin) of the DUT.