Chip I/O Test via Inner Loop Path
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Solution Overview
Problem
The high cost of external high-speed testing devices for electronic devices with high-speed bus interfaces increases the overall cost of manufacturing, as existing testing methods require expensive equipment to ensure correct input/output functions.
Innovation Solution
A system and method that establish an inner loop path within the electronic device to test input/output functions using a high-speed bus interface circuit, eliminating the need for external high-speed testing devices by utilizing a core circuit for encoding/decoding and a high-speed bus interface circuit for data transmission and reception, allowing testing at lower frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external high-speed testing device is used to test the chip, then the input/output functions can be verified, but the testing cost increases significantly
Solution Approach 1:
The chip under test performs its own self-test by establishing an inner loop path that connects its transmission mechanism to its receiving mechanism internally, eliminating the need for external high-speed testing devices. The chip tests itself using its own high-speed bus interface circuit resources.
Solution Approach 2:
The testing function is extracted from the external testing device and integrated into the chip itself through the inner loop path mechanism. The chip's transmission and receiving mechanisms work together internally to perform testing without requiring external equipment.
2Ease of manufacture
If an inner loop path is established within the chip for testing, then the testing cost is reduced, but the device complexity increases
Solution Approach 1:
The high-speed bus interface circuit serves dual purposes: it functions as a normal data transmission interface during operation and as a testing pathway when the inner loop path is established. The same transmission and receiving mechanisms are used for both normal operation and self-testing.
Solution Approach 2:
The system dynamically switches between normal operation mode and self-testing mode by establishing or disconnecting the inner loop path. The connection configuration changes based on whether testing or normal data transmission is required.
Data Source
AI summary
System and related method for testing a chip with a high-speed bus interface in a low speed testing environment is provided. The testing method for testing input/output functions of a chip includes: establishing an inner loop path between a transmission mechanism and a receiving mechanism of the chip; transmitting a testing data; and receive the testing data via the inner loop path.